TMS320VC5404
- Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
- 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
- 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
- Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
- Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
- Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
- Data Bus With a Bus Holder Feature
- Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
- On-Chip ROM
- 128K × 16-Bit (5407) Configured for Program Memory
- 64K × 16-Bit (5404) Configured for Program Memory
- On-Chip RAM
- 40K × 16-Bit (5407) Composed of Five Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
- 16K x 16-Bit (5404) Composed of Two Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
- Enhanced External Parallel Interface (XIO2)
- Single-Instruction-Repeat and Block-Repeat Operations for Program Code
- Block-Memory-Move Instructions for Better Program and Data Management
- Instructions With a 32-Bit Long Word Operand
- Instructions With Two- or Three-Operand Reads
- Arithmetic Instructions With Parallel Store and Parallel Load
- Conditional Store Instructions
- Fast Return From Interrupt
- On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank-Switching
- On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
- Two 16-Bit Timers
- Six-Channel Direct Memory Access (DMA) Controller
- Three Multichannel Buffered Serial Ports (McBSPs)
- 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
- Universal Asynchronous Receiver/Transmitter (UART) With Integrated Baud Rate Generator
- Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
- CLKOUT Off Control to Disable CLKOUT
- On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1
(JTAG) Boundary Scan Logic - 144-Pin Ball Grid Array (BGA) (GGU Suffix)
- 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
- 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
- 3.3-V I/O Supply Voltage
- 1.5-V Core Supply Voltage
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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TMS320C54x is a trademark of Texas Instruments.
This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404 (hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407 and 5404 are essentially the same device except for differences in their memory maps.
This section lists the pin assignments and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).
The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.
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기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | TMS320VC5407/TMS320VC5404 Fixed-Point Digital Signal Processors datasheet (Rev. E) | 2008/10/20 | |
| User guide | TMS320C54x Chip Support Library API Reference Guide (Rev. D) | 2003/05/05 | ||
| User guide | TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) | 2001/03/31 | ||
| User guide | TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) | 2001/01/31 | ||
| User guide | TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) | 2001/01/31 | ||
| User guide | TMS320C54x DSP Applications Guide Reference Set Volume 4 | 1996/10/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브
XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.
모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.
XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)
TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브
The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| LQFP (PGE) | 144 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치