홈 전원 관리 AC/DC 및 DC/DC 컨트롤러(외장 FET)
홈
전원 관리
AC/DC 및 DC/DC 컨트롤러(외장 FET)

TPS53626

활성

VR13 CPU VCORE 및 DDR 메모리용 2상, D-CAP+™ 스텝다운 컨트롤러

지금 주문
데이터 시트

TPS53626

활성
데이터 시트 지금 주문

제품 상세 정보

Vin (min) (V) 4.5 Vin (max) (V) 28 Iout (max) (A) 70 Operating temperature range (°C) -40 to 105 Control mode D-CAP+ Rating Catalog Vout (min) (V) 0.25 Vout (max) (V) 1.52 Features Adjustable current limit, Dynamic Voltage Scaling, Enable, Light Load Efficiency, Output discharge, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, SVID, Synchronous Rectification Iq (typ) (µA) 3500 Duty cycle (max) (%) 30 Number of phases 2
Vin (min) (V) 4.5 Vin (max) (V) 28 Iout (max) (A) 70 Operating temperature range (°C) -40 to 105 Control mode D-CAP+ Rating Catalog Vout (min) (V) 0.25 Vout (max) (V) 1.52 Features Adjustable current limit, Dynamic Voltage Scaling, Enable, Light Load Efficiency, Output discharge, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, SVID, Synchronous Rectification Iq (typ) (µA) 3500 Duty cycle (max) (%) 30 Number of phases 2
VQFN (RSM) 32 16 mm² 4 x 4
  • Intel VR13 Serial VID (SVID) Compliant
  • 1- or 2-Phase Operation
  • Default Configuration Mode for VR13 VCCIO and VMCP
  • Supports Both Droop and Non-Droop Applications
  • 8-Bit DAC with 5-mV Step
  • Output Range: 0.25 V to 1.52 V
  • Optimized Efficiency at Light and Heavy Loads
  • 8 Independent Levels of Overshoot Reduction (OSR) and Undershoot Reduction (USR)
  • Driverless Configuration for Efficient High-Frequency Switching
  • Supports Discrete, Power Block, Power Stage or DrMOS MOSFET Implementations
  • Accurate, Adjustable Voltage Positioning
  • 300-kHz to 1-MHz Frequency Selections
  • Patented AutoBalance Phase Balancing
  • Programmable ON-Pulse Extension for Load Transient Boost
  • Programmable Auto DCM and CCM Operation
  • Selectable 8-level Current Limit
  • 4.5-V to 28-V Conversion Voltage Range
  • Small, 4 mm × 4 mm, 32-Pin, VQFN PowerPad Package
  • Intel VR13 Serial VID (SVID) Compliant
  • 1- or 2-Phase Operation
  • Default Configuration Mode for VR13 VCCIO and VMCP
  • Supports Both Droop and Non-Droop Applications
  • 8-Bit DAC with 5-mV Step
  • Output Range: 0.25 V to 1.52 V
  • Optimized Efficiency at Light and Heavy Loads
  • 8 Independent Levels of Overshoot Reduction (OSR) and Undershoot Reduction (USR)
  • Driverless Configuration for Efficient High-Frequency Switching
  • Supports Discrete, Power Block, Power Stage or DrMOS MOSFET Implementations
  • Accurate, Adjustable Voltage Positioning
  • 300-kHz to 1-MHz Frequency Selections
  • Patented AutoBalance Phase Balancing
  • Programmable ON-Pulse Extension for Load Transient Boost
  • Programmable Auto DCM and CCM Operation
  • Selectable 8-level Current Limit
  • 4.5-V to 28-V Conversion Voltage Range
  • Small, 4 mm × 4 mm, 32-Pin, VQFN PowerPad Package

The TPS53626 device is a driverless, VR13 SVID compliant, synchronous buck controller.Advanced control features such as D-CAP+ architecture with overlapping pulse support undershoot reduction (USR) and overshoot reduction (OSR) provide fasttransient response, lowest output capacitance and high efficiency. The device also supportssingle-phase operation in CCM or DCM for light-load efficiency boost. The device integrates a fullset of VR13 I/O features including VR_READY (PGOOD), ALERT and VR_HOT. The SVID interface address allows programming from 00h to 07h.Adjustable control of VOUT slew rate can be programmed as high as20mV/uS.

Paired with the TI NexFET Power Stage, this totalsolution delivers exceptionally high speed and low switching loss. The TPS53626 also offers four default modes that configure VCCIO and VMCP settings with one single external resistor to savecomponent count and board space.

The TPS53626 device package is a space saving, thermally enhanced 32-pin VQFN packagethat operates from –40°C to 105°C.

For all available packages, see the orderable addendum at the end of the document.

The TPS53626 device is a driverless, VR13 SVID compliant, synchronous buck controller.Advanced control features such as D-CAP+ architecture with overlapping pulse support undershoot reduction (USR) and overshoot reduction (OSR) provide fasttransient response, lowest output capacitance and high efficiency. The device also supportssingle-phase operation in CCM or DCM for light-load efficiency boost. The device integrates a fullset of VR13 I/O features including VR_READY (PGOOD), ALERT and VR_HOT. The SVID interface address allows programming from 00h to 07h.Adjustable control of VOUT slew rate can be programmed as high as20mV/uS.

Paired with the TI NexFET Power Stage, this totalsolution delivers exceptionally high speed and low switching loss. The TPS53626 also offers four default modes that configure VCCIO and VMCP settings with one single external resistor to savecomponent count and board space.

The TPS53626 device package is a space saving, thermally enhanced 32-pin VQFN packagethat operates from –40°C to 105°C.

For all available packages, see the orderable addendum at the end of the document.
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기술 자료

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1개 모두 보기
유형 직함 날짜
* Data sheet 2-Phase, D-CAP+™ Step-Down Controller for VR13 CPU VCORE and DDR Memory datasheet 2015/07/09

설계 및 개발

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패키지 핀 CAD 기호, 풋프린트 및 3D 모델
VQFN (RSM) 32 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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포럼 주제 모두 보기(영문)

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