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微控制器 (MCU) 與處理器
Arm 式處理器

AM1806

現行

Sitara 處理器：Arm9、LPDDR、DDR2、顯示器

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AM1806

現行
產品規格表 立即訂購

產品詳細資料

Arm CPU 1 Arm9 Arm (max) (MHz) 375, 456 Coprocessors PRU-ICSS CPU 32-bit Display type 1 LCD Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
Arm CPU 1 Arm9 Arm (max) (MHz) 375, 456 Coprocessors PRU-ICSS CPU 32-bit Display type 1 LCD Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
NFBGA (ZCE) 361 169 mm² 13 x 13 NFBGA (ZWT) 361 256 mm² 16 x 16
  • 375- and 456-MHz ARM926EJ-S RISC MPU
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
      • Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Transmit and Receive Clocks
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
  • 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Commercial or Extended Temperature
  • 375- and 456-MHz ARM926EJ-S RISC MPU
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
      • Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Transmit and Receive Clocks
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
  • 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Commercial or Extended Temperature

The AM1806 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The universal parallel port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) is included providing a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.

The AM1806 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The universal parallel port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) is included providing a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.
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類型 標題 日期
* Data sheet AM1806 ARM Microprocessor datasheet (Rev. F) PDF | HTML 2014年 3月 21日
* Errata AM1806 ARM Microprocessor Silicon Errata (Revs 2.3, 2.1 and 2.0) (Rev. H) 2014年 9月 17日
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 2023年 3月 30日
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 2023年 3月 30日
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
Application note Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x 2019年 12月 20日
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019年 6月 3日
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019年 6月 3日
Application note Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx 2019年 4月 25日
Application note General Hardware Design/BGA PCB Design/BGA 2019年 2月 22日
Application note OMAP-L13x / C674x / AM1x schematic review guidelines PDF | HTML 2019年 2月 14日
Application note Using the AM18xx Bootloader (Rev. D) PDF | HTML 2019年 1月 22日
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018年 11月 19日
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018年 11月 19日
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018年 9月 24日
User guide PRU Assembly Instruction User Guide 2018年 2月 16日
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018年 1月 16日
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018年 1月 16日
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017年 9月 30日
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017年 9月 30日
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017年 6月 21日
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017年 6月 21日
User guide AM1806 ARM Microprocessor Technical Reference Manual (Rev. C) 2016年 9月 12日
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016年 4月 30日
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016年 4月 30日
Technical article Spring has sprung. A sale has sprung. PDF | HTML 2016年 4月 4日
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014年 11月 5日
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014年 11月 5日
Application note AM18xx Pin Multiplexing Utility (Rev. A) 2011年 12月 6日
Application note Powering the AM1806, AM1808, and AM1810 with the TPS650061 2011年 9月 6日
Application note High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS (Rev. C) 2011年 8月 29日
Application note Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO (Rev. B) 2011年 8月 29日
Application note Powering OMAP-L132/L138, C6742/4/6, and AM18x with TPS65070 (Rev. B) 2011年 8月 29日
Application note Simple Power Solution Using LDOs (Rev. B) 2011年 8月 29日
Application note AM18x power consumption summary 2010年 8月 30日
Application note High-Efficiency Power Solution Using DC/DC Converters With DVFS (Rev. A) 2010年 5月 5日
Application note High-Integration, High-Efficiency Power Solution Using DC/DC Converters w/DVFS (Rev. A) 2010年 5月 5日
Application note TMS320C6748/46/42 & OMAP-L132/L138 USB Downstream Host Compliance Testing 2009年 8月 17日
Application note TMS320C6748/46/42 & OMAP-L1x8 USB Upstream Device Compliance Testing 2009年 8月 17日
Application note TMS320C674x/OMAP-L1x USB Compliance Checklist 2009年 3月 12日
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日

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XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比，XDS200 是兼具低成本與優異效能的完美平衡，可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

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XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

LINUXEZSDK-AM18X — Linux EZ SDK for AM1808, AM1806, AM1802

SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

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LINUXSDK-AM17X — Linux SDK for AM1707, AM1705

SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

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PRU-SWPKG — Programmable Real-time Unit (PRU) Software Support Package

The PRU Software Support Package is an add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit sub-system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors.  The PRU-ICSS achieves deterministic, real-time (...)

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AM1802 — Sitara 處理器：Arm9、LPDDR、DDR2 乙太網路 AM1806 — Sitara 處理器：Arm9、LPDDR、DDR2、顯示器 AM1808 — Sitara 處理器：Arm9、LPDDR、DDR2、顯示器、乙太網路 AM1810 — Sitara 處理器：Arm9、LPDDR、DDR2、顯示器、乙太網路、PROFIBUS AM4377 — Sitara 處理器：Arm Cortex-A9、PRU-ICSS、EtherCAT AM4378 — Sitara 處理器：ARM Cortex-A9、PRU-ICSS、3D 繪圖
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WINCESDK-AM1XOMAPL1X — Windows® 嵌入式 Compact/CE SDK - ARM9™ 型 AM18x、OMAP-L13x 處理器

Microsoft Windows Embedded Compact (WEC7) andCE (WinCE 6.0) operating systems are optimized for embedded devices that require minimum storage based on a componentized architecture.

WinCE BSPs for ARM9-based processors are now available fromAdeneo Embedded.

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STARTERWARE-AM18X — StarterWare for AM18x Processors

StarterWare provides C-based no-OS platform support for TI's ARM9™ and ARM® Cortex™ A8 based devices. StarterWare provides device abstraction layer libraries, peripheral programming examples such as Ethernet, graphics and USB, and board level example applications. StarterWare can be (...)

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STARTERWARE-AM335X — StarterWare for AM335x Processors

StarterWare provides C-based no-OS platform support for TI's ARM9™ and ARM® Cortex™ A8 based devices. StarterWare provides device abstraction layer libraries, peripheral programming examples such as Ethernet, graphics and USB, and board level example applications. StarterWare can be (...)

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

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作業系統 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
從：Mentor Graphics Corporation
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支援軟體

SPRC940.ZIP — PRU Software Development Package [XP]

The PRU Software Support Package is an add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit sub-system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors.  The PRU-ICSS achieves deterministic, real-time (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
AM1806 — Sitara 處理器：Arm9、LPDDR、DDR2、顯示器 AM1810 — Sitara 處理器：Arm9、LPDDR、DDR2、顯示器、乙太網路、PROFIBUS
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模擬型號

AM1806 ZCE BSDL

SPRM482.ZIP (8 KB) - BSDL Model
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模擬型號

AM1806 ZCE IBIS Model (Rev. A)

SPRM483A.ZIP (120 KB) - IBIS Model
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模擬型號

AM1806 ZWT BSDL Model

SPRM484.ZIP (8 KB) - BSDL Model
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模擬型號

AM1806 ZWT IBIS Model (Rev. A)

SPRM485A.ZIP (121 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZCE) 361 Ultra Librarian
NFBGA (ZWT) 361 Ultra Librarian
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  • 產品標記
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  • 認證摘要
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