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TMUX4052 現行 具有 1.8-V 邏輯相容邏輯元件的 +/-12-V、4:1、2 通道多工器 24-V mux with 1.8-V logic and smaller package options

產品詳細資料

Configuration 4:1 Number of channels 2 Power supply voltage - single (V) 3.3, 5, 12, 16, 20 Power supply voltage - dual (V) +/-10, +/-2.5, +/-5 Protocols Analog Ron (typ) (Ω) 125 CON (typ) (pF) 18 ON-state leakage current (max) (µA) 0.3 Supply current (typ) (µA) 0.04 Bandwidth (MHz) 25 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 10 Rating Catalog Drain supply voltage (max) (V) 20 Supply voltage (max) (V) 20 Negative rail supply voltage (max) (V) 0
Configuration 4:1 Number of channels 2 Power supply voltage - single (V) 3.3, 5, 12, 16, 20 Power supply voltage - dual (V) +/-10, +/-2.5, +/-5 Protocols Analog Ron (typ) (Ω) 125 CON (typ) (pF) 18 ON-state leakage current (max) (µA) 0.3 Supply current (typ) (µA) 0.04 Bandwidth (MHz) 25 Operating temperature range (°C) -55 to 125 Features Break-before-make Input/output continuous current (max) (mA) 10 Rating Catalog Drain supply voltage (max) (V) 20 Supply voltage (max) (V) 20 Negative rail supply voltage (max) (V) 0
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Wide range of digital and analog signal levels:
    • Digital: 3V to 20V
    • Analog: ≤ 20VP-P
  • Low ON resistance, 125Ω (typical) over 15VP-P signal input range for VDD – VEE = 18V
  • High OFF resistance, channel leakage of ±10pA (typical) at VDD – VEE = 18V
  • Logic-level conversion for digital addressing signals of 3V to 20V (VDD – VSS = 3V to 20V) to switch analog signals to 20VP-P (VDD – VEE = 20V) matched switch characteristics, rON = 5Ω (typical) for VDD – VEE = 15V very low quiescent power dissipation under all digital-control input and supply conditions, 0.2µW (typical) at VDD – VSS = VDD – VEE = 10V
  • Binary address decoding on chip
  • 5V, 10V, and 15V parametric ratings
  • 100% tested for quiescent current at 20V
  • Maximum input current of 1µA at 18V over full package temperature range, 100nA at 18V and 25°C
  • Break-before-make switching eliminates channel overlap
  • Wide range of digital and analog signal levels:
    • Digital: 3V to 20V
    • Analog: ≤ 20VP-P
  • Low ON resistance, 125Ω (typical) over 15VP-P signal input range for VDD – VEE = 18V
  • High OFF resistance, channel leakage of ±10pA (typical) at VDD – VEE = 18V
  • Logic-level conversion for digital addressing signals of 3V to 20V (VDD – VSS = 3V to 20V) to switch analog signals to 20VP-P (VDD – VEE = 20V) matched switch characteristics, rON = 5Ω (typical) for VDD – VEE = 15V very low quiescent power dissipation under all digital-control input and supply conditions, 0.2µW (typical) at VDD – VSS = VDD – VEE = 10V
  • Binary address decoding on chip
  • 5V, 10V, and 15V parametric ratings
  • 100% tested for quiescent current at 20V
  • Maximum input current of 1µA at 18V over full package temperature range, 100nA at 18V and 25°C
  • Break-before-make switching eliminates channel overlap

The CD405xB analog multiplexers and demultiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE supply-voltage ranges, independent of the logic state of the control signals.

The CD405xB analog multiplexers and demultiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE supply-voltage ranges, independent of the logic state of the control signals.

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類型 標題 日期
* Data sheet CD405xB CMOS Single 8-Channel Analog Multiplexer or Demultiplexer With Logic-Level Conversion datasheet (Rev. M) PDF | HTML 2024年 11月 15日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Application note CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. C) PDF | HTML 2021年 11月 19日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日

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介面轉接器

LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

使用指南: PDF
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

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