首頁 時鐘與計時 時鐘抖動清除器
首頁
時鐘與計時
時鐘抖動清除器

CDCE813-Q1

現行

具有 2.5-V 和 3.3-V 輸出的可編程 1-PLL 時鐘合成器和抖動消除器

立即訂購
產品規格表

CDCE813-Q1

現行
產品規格表 立即訂購

產品詳細資料

Function Single-loop PLL Number of outputs 3 RMS jitter (fs) 50000 Output frequency (min) (MHz) 0.07 Output frequency (max) (MHz) 230 Input type LVCMOS (REF_CLK) Output type LVCMOS Supply voltage (min) (V) 1.7 Supply voltage (max) (V) 3.6 Features Integrated EEPROM Rating Automotive Operating temperature range (°C) -40 to 105 Number of input channels 1
Function Single-loop PLL Number of outputs 3 RMS jitter (fs) 50000 Output frequency (min) (MHz) 0.07 Output frequency (max) (MHz) 230 Input type LVCMOS (REF_CLK) Output type LVCMOS Supply voltage (min) (V) 1.7 Supply voltage (max) (V) 3.6 Features Integrated EEPROM Rating Automotive Operating temperature range (°C) -40 to 105 Number of input channels 1
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 2: –40°C to 105°C ambient operating temperature range
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C6
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230 MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter (typical 50ps)
  • 1.8V device power supply (core voltage)
  • Separate output supply pins: 3.3V and 2.5V
  • Flexible clock driver
    • Three user-definable control inputs [S0, S1, S2], for example, SSC selection, frequency switching, output enable, or power down
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet, and GPS
    • Generates common clock frequencies used with TI- DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0PPM clock generation
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI ClockPro™ programming software)
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 2: –40°C to 105°C ambient operating temperature range
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C6
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230 MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter (typical 50ps)
  • 1.8V device power supply (core voltage)
  • Separate output supply pins: 3.3V and 2.5V
  • Flexible clock driver
    • Three user-definable control inputs [S0, S1, S2], for example, SSC selection, frequency switching, output enable, or power down
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet, and GPS
    • Generates common clock frequencies used with TI- DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0PPM clock generation
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI ClockPro™ programming software)

The CDCE813-Q1 device is a modular Phase-locked-loop-based (PLL), low-cost, high-performance, programmable clock synthesizers. They generate up to three output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using the integrated configurable PLL.

The CDCE813-Q1 has separate output supply pins, VDDOUT, providing 2.5V to 3.3V.

The input accepts an external crystal or LVCMOS clock signal. A selectable on-chip VCXO allows synchronization of the output frequency to an external control signal.

The PLL supports SSC (spread-spectrum clocking) for better electromagnetic interference (EMI) performance.

The device supports nonvolatile EEPROM programming for easy customization of the device to the application. All device settings are programmable through the I2C bus, a 2-wire serial interface.

The CDCE813-Q1 operates in a 1.8V core environment as well as eliminating the need for additional, independent XTAL oscillators which reduces component count and board size. The device operates in a temperature range of –40°C to 105°C.

The CDCE813-Q1 device is a modular Phase-locked-loop-based (PLL), low-cost, high-performance, programmable clock synthesizers. They generate up to three output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using the integrated configurable PLL.

The CDCE813-Q1 has separate output supply pins, VDDOUT, providing 2.5V to 3.3V.

The input accepts an external crystal or LVCMOS clock signal. A selectable on-chip VCXO allows synchronization of the output frequency to an external control signal.

The PLL supports SSC (spread-spectrum clocking) for better electromagnetic interference (EMI) performance.

The device supports nonvolatile EEPROM programming for easy customization of the device to the application. All device settings are programmable through the I2C bus, a 2-wire serial interface.

The CDCE813-Q1 operates in a 1.8V core environment as well as eliminating the need for additional, independent XTAL oscillators which reduces component count and board size. The device operates in a temperature range of –40°C to 105°C.
filter 尋找其它 時鐘抖動清除器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet CDCE813-Q1 Programmable 1-PLL Clock Synthesizer and Jitter Cleaner With 2.5V and 3.3V Outputs datasheet (Rev. D) PDF | HTML 2024年 2月 8日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

CDCE813 IBIS Model

SNAM227.ZIP (27 KB) - IBIS Model
下載
設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
立即進行設計
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 14 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片