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TLV9102 現行 雙路、16V、1.1MHz、低功耗運算放大器 Pin-to-pin upgrade with improved performance: lower Vos(1.5mV), higher slew rate(4.5V/us) and output current(80mA)

產品詳細資料

Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 15.5 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Rail-to-rail In to V-, Out GBW (typ) (MHz) 1.4 Slew rate (typ) (V/µs) 1.1 Vos (offset voltage at 25°C) (max) (mV) 9 Iq per channel (typ) (mA) 0.38 Vn at 1 kHz (typ) (nV√Hz) 22 Rating Catalog Operating temperature range (°C) -40 to 85 Offset drift (typ) (µV/°C) 2.3 Input bias current (max) (pA) 0.4 CMRR (typ) (dB) 83 Iout (typ) (A) 0.04 Architecture CMOS Input common mode headroom (to negative supply) (typ) (V) -0.4 Input common mode headroom (to positive supply) (typ) (V) -1.9 Output swing headroom (to negative supply) (typ) (V) 0.1 Output swing headroom (to positive supply) (typ) (V) -0.13
Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 15.5 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Rail-to-rail In to V-, Out GBW (typ) (MHz) 1.4 Slew rate (typ) (V/µs) 1.1 Vos (offset voltage at 25°C) (max) (mV) 9 Iq per channel (typ) (mA) 0.38 Vn at 1 kHz (typ) (nV√Hz) 22 Rating Catalog Operating temperature range (°C) -40 to 85 Offset drift (typ) (µV/°C) 2.3 Input bias current (max) (pA) 0.4 CMRR (typ) (dB) 83 Iout (typ) (A) 0.04 Architecture CMOS Input common mode headroom (to negative supply) (typ) (V) -0.4 Input common mode headroom (to positive supply) (typ) (V) -1.9 Output swing headroom (to negative supply) (typ) (V) 0.1 Output swing headroom (to positive supply) (typ) (V) -0.13
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Specified for 2kΩ and 600Ω loads
  • High voltage gain: 126dB, 2kΩ
  • Low offset voltage drift: 2.3µV/°C
  • Ultra-low input bias current: 40fA
  • Input common-mode range includes V−
  • Operates on standard 5V and 15V supplies
  • IQ = 375µA/amplifier; independent of V+
  • Low noise: 22nV/√Hz
  • Slew rate: 1.1V/µs
  • Improved performance over TLC272
  • Specified for 2kΩ and 600Ω loads
  • High voltage gain: 126dB, 2kΩ
  • Low offset voltage drift: 2.3µV/°C
  • Ultra-low input bias current: 40fA
  • Input common-mode range includes V−
  • Operates on standard 5V and 15V supplies
  • IQ = 375µA/amplifier; independent of V+
  • Low noise: 22nV/√Hz
  • Slew rate: 1.1V/µs
  • Improved performance over TLC272

The dual LMC6032 and quad LMC6034 (LMC603x) are CMOS operational amplifiers that operate from either a single supply or dual supplies. Device performance features include an input common-mode range that reaches ground, low input bias current, and high voltage gain into realistic loads, such as 2kΩ and 600Ω.

This chip is built with TI’s advanced CMOS process.

For higher-performance characteristics, see the OPA928.

The dual LMC6032 and quad LMC6034 (LMC603x) are CMOS operational amplifiers that operate from either a single supply or dual supplies. Device performance features include an input common-mode range that reaches ground, low input bias current, and high voltage gain into realistic loads, such as 2kΩ and 600Ω.

This chip is built with TI’s advanced CMOS process.

For higher-performance characteristics, see the OPA928.

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類型 標題 日期
* Data sheet LMC603x CMOS Dual Operational Amplifiers datasheet (Rev. D) PDF | HTML 2024年 2月 28日
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日

設計與開發

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開發板

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AMP-PDK-EVM 套件支援五種最熱門的業界標準封裝,包括:

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開發板

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使用指南: PDF
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開發板

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The DUAL-DIYAMP-EVM is a unique evaluation module (EVM) family that provides engineers and do it yourselfers (DIYers) with real-world amplifier circuits, enabling you to quickly evaluate design concepts and verify simulations. It is designed specifically for dual package op amps in the (...)
使用指南: PDF
TI.com 無法提供
模擬型號

LMC6032 PSPICE Model

SNOM182.ZIP (1 KB) - PSpice Model
計算工具

ANALOG-ENGINEER-CALC — 類比工程師計算機

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設計工具

CIRCUIT060013 — 具有 T 網路回饋電路的反相放大器

此設計可反轉輸入訊號 VIN,並使用 1000 V/V 或 60 dB 訊號增益。具有 T 回饋網路的反相放大器可在沒有較小 R4 值或超大回饋電阻器值的情況下獲得高增益。
設計工具

CIRCUIT060015 — 可調式參考電壓電路

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設計工具

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

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使用指南: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
PDIP (P) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian

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  • 鉛塗層/球物料
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  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
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