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The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.
The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.
The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | LMH0341/041/071/051 3Gbps, HD, SD, DVB-ASI SDI Deserializr w/Loopthru & LVDS I/F datasheet (Rev. Q) | 2013年 4月 16日 | |
| Selection guide | Broadcast and Professional Video Interface Solutions (Rev. E) | 2017年 4月 5日 | ||
| Application note | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 2013年 4月 26日 | ||
| Application note | AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) | 2013年 4月 26日 | ||
| Application note | AN-2145 Power Considerations for SDI Products (Rev. B) | 2013年 4月 26日 | ||
| Application note | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 2013年 4月 26日 | ||
| Application note | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 2009年 11月 12日 | ||
| Application note | A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video | 2008年 3月 18日 |
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We have developed a family of serializers and deserializers intended to support the serial digital interface (SDI) standards of the Society of Motion Picture and Television Engineers (SMPTE). These devices connect to a host FPGA through a moderate speed, moderate width (600 Mbps, 5 bits wide) (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |