LP2995
- Low Output Voltage Offset
- Works with +5v, +3.3v and 2.5v Rails
- Source and Sink Current
- Low External Component Count
- No External Resistors Required
- Linear Topology
- Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages
- Low Cost and Easy to Use
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The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.
技術文件
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檢視所有 6 類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | LP2995 DDR Termination Regulator datasheet (Rev. M) | 2013年 3月 19日 | |
White paper | Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) | PDF | HTML | 2024年 4月 30日 | |
Application note | Limiting DDR Termination Regulators’ Inrush Current | 2016年 8月 23日 | ||
EVM User's guide | AN-1241 LP2995 Evaluation Board (Rev. B) | 2013年 5月 7日 | ||
Application note | AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) | 2013年 5月 6日 | ||
Application note | DDR-SDRAM Termination Simplified Using A Linear Regulator | 2002年 7月 23日 |
設計與開發
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參考設計
TIDA-010011 — 用於保護繼電器處理器模組的高效電源供應架構參考設計
This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
HSOIC (DDA) | 8 | Ultra Librarian |
SOIC (D) | 8 | Ultra Librarian |
WQFN (NHP) | 16 | Ultra Librarian |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。