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SN74CBT3383C

現行

具有 –2-V 未達目標保護的 5-V、交叉點/交換、10 通道 FET 匯流排開關

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產品規格表

SN74CBT3383C

現行
產品規格表 立即訂購

產品詳細資料

Configuration Crosspoint/exchange Number of channels 10 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 3 CON (typ) (pF) 18.5 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Undershoot protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration Crosspoint/exchange Number of channels 10 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 3 CON (typ) (pF) 18.5 Bandwidth (MHz) 200 Operating temperature range (°C) -40 to 85 Features Undershoot protection Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SSOP (DBQ) 24 51.9 mm² 8.65 x 6 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Undershoot protection for off-isolation on A and B ports up to −2 V
  • Bidirectional data flow, with near-zero propagation delay
  • Low on-state resistance (ron) characteristics (ron = 3 Ω typical)
  • Low input output capacitance minimizes loading and signal distortion (Cio (OFF) = 8 pF typical)
  • Data and control inputs provide undershoot clamp diodes
  • Low power consumption (ICC = 3 µA maximum)
  • VCC operating range from 4 V to 5.5 V data I/Os support 0 to 5-V signaling levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V)
  • Control inputs can be driven by TTL or 5-V/3.3-V CMOS outputs
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD performance tested per JESD 22− 2000-V Human-Body Model (A114-B, Class II)− 1000-V Charged-Device Model (C101)
  • Supports both digital and analog applications: PCI interface, memory interleaving, bus isolation, low-distortion signal gating
  • Undershoot protection for off-isolation on A and B ports up to −2 V
  • Bidirectional data flow, with near-zero propagation delay
  • Low on-state resistance (ron) characteristics (ron = 3 Ω typical)
  • Low input output capacitance minimizes loading and signal distortion (Cio (OFF) = 8 pF typical)
  • Data and control inputs provide undershoot clamp diodes
  • Low power consumption (ICC = 3 µA maximum)
  • VCC operating range from 4 V to 5.5 V data I/Os support 0 to 5-V signaling levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V)
  • Control inputs can be driven by TTL or 5-V/3.3-V CMOS outputs
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD performance tested per JESD 22− 2000-V Human-Body Model (A114-B, Class II)− 1000-V Charged-Device Model (C101)
  • Supports both digital and analog applications: PCI interface, memory interleaving, bus isolation, low-distortion signal gating

The SN74CBT3383C is a high-speed TTL-compatible FET bus-exchange switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3383C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3383C is organized as a 10-bit bus switch, or as a 5-bit bus-exchange switch with a single output-enable (BE) input that provides data exchanging between four signal ports. The select (BX) input controls the data path of the bus-exchange switch. When BE is low, the A port is connected to the B port, allowing bidirectional data flow between ports. When BE is high, a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, BE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBT3383C is a high-speed TTL-compatible FET bus-exchange switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3383C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3383C is organized as a 10-bit bus switch, or as a 5-bit bus-exchange switch with a single output-enable (BE) input that provides data exchanging between four signal ports. The select (BX) input controls the data path of the bus-exchange switch. When BE is low, the A port is connected to the B port, allowing bidirectional data flow between ports. When BE is high, a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, BE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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類型 標題 日期
* Data sheet SN74CBT3383C 10-Bit FET Bus-Exchange Switch 5-V Bus SwitchWith −2-V Undershoot Protection datasheet (Rev. A) PDF | HTML 2022年 12月 2日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Application note CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. C) PDF | HTML 2021年 11月 19日
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021年 1月 6日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
More literature Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日

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The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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