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SN74CBTLV3861 現行 具有 1 個控制輸入的 3.3-V、1:1 (SPST)、10 通道通用型 FET 匯流排開關 Higher bandwidth

產品詳細資料

Configuration 1:1 SPST Number of channels 10 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 20 Operating temperature range (°C) -40 to 85 Features Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 1:1 SPST Number of channels 10 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 20 Operating temperature range (°C) -40 to 85 Features Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SSOP (DB) 24 63.96 mm² 8.2 x 7.8 SSOP (DBQ) 24 51.9 mm² 8.65 x 6 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4 TVSOP (DGV) 24 32 mm² 5 x 6.4
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Designed to Be Used in Level-Shifting Applications

  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Designed to Be Used in Level-Shifting Applications

The SN74CBTD3861 provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. A diode to VCC is integrated on the die to allow for level shifting from 5-V signals at the device inputs to 3.3-V signals at the device outputs.

The device is organized as one 10-bit switch with a single output-enable (OE)\ input. When (OE)\ is low, the switch is on, and port A is connected to port B. When (OE)\ is high, the switch is open, and the high-impedance state exists between the two ports.

The SN74CBTD3861 provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. A diode to VCC is integrated on the die to allow for level shifting from 5-V signals at the device inputs to 3.3-V signals at the device outputs.

The device is organized as one 10-bit switch with a single output-enable (OE)\ input. When (OE)\ is low, the switch is on, and port A is connected to port B. When (OE)\ is high, the switch is open, and the high-impedance state exists between the two ports.

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類型 標題 日期
* Data sheet 10-Bit FET Bus Switch With Level Shifting datasheet (Rev. G) 2002年 7月 24日

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

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