產品詳細資料

Technology family LV1T Applications GPIO Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -8 IOL (max) (mA) -8 Supply current (max) (µA) 5.5 Features 4.2, 4.64 Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV1T Applications GPIO Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -8 IOL (max) (mA) -8 Supply current (max) (µA) 5.5 Features 4.2, 4.64 Input type TTL-Compatible CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Latch-up performance exceeds 250mA per JESD 17
  • Single-supply voltage translator at 5V, 3.3V, 2.5V, and 1.8V VCC
  • Operating range of 1.65V to 5.5V
  • Up translation:
    • 1.2V(1) to 1.8V at 1.8V VCC
    • 1.5V(1) to 2.5V at 2.5V VCC
    • 1.8V(1) to 3.3V at 3.3V VCC
    • 3.3V to 5.0V at 5.0V VCC
  • Down translation:
    • 3.3V to 1.8V at 1.8V VCC
    • 3.3V to 2.5V at 2.5V VCC
    • 5.0V to 3.3V at 3.3V VCC
  • Logic output is referenced to VCC
  • Output drive:
    • 8mA output drive at 5V
    • 7mA output drive at 3.3V
    • 3mA output drive at 1.8V
  • Characterized up to 50MHz at 3.3V VCC
  • 5V Tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Supports standard logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families (1)

(1)Refer to the VIH/VIL and output drive for lower VCC condition.

  • Latch-up performance exceeds 250mA per JESD 17
  • Single-supply voltage translator at 5V, 3.3V, 2.5V, and 1.8V VCC
  • Operating range of 1.65V to 5.5V
  • Up translation:
    • 1.2V(1) to 1.8V at 1.8V VCC
    • 1.5V(1) to 2.5V at 2.5V VCC
    • 1.8V(1) to 3.3V at 3.3V VCC
    • 3.3V to 5.0V at 5.0V VCC
  • Down translation:
    • 3.3V to 1.8V at 1.8V VCC
    • 3.3V to 2.5V at 2.5V VCC
    • 5.0V to 3.3V at 3.3V VCC
  • Logic output is referenced to VCC
  • Output drive:
    • 8mA output drive at 5V
    • 7mA output drive at 3.3V
    • 3mA output drive at 1.8V
  • Characterized up to 50MHz at 3.3V VCC
  • 5V Tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Supports standard logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families (1)

(1)Refer to the VIH/VIL and output drive for lower VCC condition.

The SN74LV1T34 is a single buffer gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T34 is a single buffer gate with reduced input thresholds to support voltage translation applications.

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類型 標題 日期
* Data sheet SN74LV1T34 Single Power Supply Single Buffer GATE CMOS Logic Level Shifter datasheet (Rev. E) PDF | HTML 2024年 2月 8日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 2024年 5月 14日
Application brief Enabling Modular PLC System Designs with Single-Supply Level Translation PDF | HTML 2024年 4月 16日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
TI.com 無法提供
模擬型號

SN74LV1T34 Behavioral SPICE Model

SCLM180.ZIP (7 KB) - PSpice Model
模擬型號

SN74LV1T34 IBIS Model

SCLM119.ZIP (49 KB) - IBIS Model
參考設計

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This reference design uses our SimpleLink Wi-Fi CC3200 internet-on-a-chip wireless MCU module to create a data bridge between existing hardware with a logic-level UART interface and a Wi-Fi network. The design also contains a simple switcher power supply with a wide-input range suitable (...)
Design guide: PDF
電路圖: PDF
參考設計

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This reference design provides a processing foundation for a cascaded imaging radar system. Cascade radar devices can support front, long-range (LRR) beam-forming applications as well as corner- and side-cascade radar and sensor fusion systems. This reference design provides qualified developers (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010032 — 通用資料集中器參考設計,支援乙太網路、6LoWPAN 射頻網格及其他

IPv6-based grid communications are becoming the standard choice in industrial markets and applications like smart meters and grid automation. The universal data concentrator design provides a complete IPv6-based network solution integrated with Ethernet backbone communication, 6LoWPAN RF mesh (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010085 — 使用數位隔離器的 24-VAC 多通道固態繼電器參考設計

此參考設計展示使用單一隔離的多通道固態繼電器 (SSR)。此設計採用含單一隔離式電源供應器與通用接地閘極驅動電路的多通道數位隔離器,以獨立控制多個 SSR。此設計適用 24-VAC 供電繼電器,額定電流可達 2A,但可擴充至 240VAC 和更高的額定電流。每個 SSR 通道消耗的空間小於 75 mm 2,組件的最大高度約爲 3 mm,與機電繼電器相比,可大幅節省尺寸。使用單一隔離式電源可減少機板空間及 BOM 成本。
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00580 — 通過車規認證的 16 位元旋轉相位差編碼器參考設計

People prefer to use knobs over touchscreens in many situations.  This solution minimizes the required connections to a microcontroller to monitor a rotary quadrature encoder's direction and distance of rotation.
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23 (DBV) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian

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  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
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