產品詳細資料

Technology family LV1T Applications GPIO, SPI Bits (#) 6 Configuration 6 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -8 IOL (max) (mA) 8 Features Balanced outputs, Single supply Input type TTL-Compatible CMOS Output type Balanced CMOS, Open-drain Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV1T Applications GPIO, SPI Bits (#) 6 Configuration 6 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -8 IOL (max) (mA) 8 Features Balanced outputs, Single supply Input type TTL-Compatible CMOS Output type Balanced CMOS, Open-drain Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Wide operating range of 1.65 V to 5.5 V
  • 5.5-V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
    • Up translation from 1.2 V to 5 V with 1.8-V supply
    • Down translation from 5 V to 0.8 V or even less with any valid supply
  • 5.5-V tolerant input pins
  • Supports standard function pinout
  • Latch-up performance exceeds 250 mA per JESD 17
  • Wide operating range of 1.65 V to 5.5 V
  • 5.5-V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
    • Up translation from 1.2 V to 5 V with 1.8-V supply
    • Down translation from 5 V to 0.8 V or even less with any valid supply
  • 5.5-V tolerant input pins
  • Supports standard function pinout
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV6T06 device contains six independent inverters with open-drain outputs. Each inverter performs the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV6T06 device contains six independent inverters with open-drain outputs. Each inverter performs the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

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類型 標題 日期
* Data sheet SN74LV6T06 Hex Open-Drain Inverters with Integrated Translation datasheet PDF | HTML 2023年 8月 21日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Application brief Enabling Modular PLC System Designs with Single-Supply Level Translation PDF | HTML 2024年 4月 16日

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TSSOP (PW) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian

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