SN74LVC1G08
- Available in the Ultra Small 0.64-mm2
Package (DPW) With 0.5-mm Pitch - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Provides Down Translation to VCC
- Max tpd of 3.6 ns at 3.3 V
- Low Power Consumption, 10-µA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
- Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G08 device performs the Boolean function or in positive logic.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.
The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.
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封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
DSBGA (YZP) | 5 | Ultra Librarian |
SOT-23 (DBV) | 5 | Ultra Librarian |
SOT-5X3 (DRL) | 5 | Ultra Librarian |
SOT-SC70 (DCK) | 5 | Ultra Librarian |
USON (DRY) | 6 | Ultra Librarian |
X2SON (DPW) | 5 | Ultra Librarian |
X2SON (DSF) | 6 | Ultra Librarian |
訂購與品質
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- RoHS
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- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
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