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Arm 式處理器

TMS320DM8127

現行

DaVinci 數位媒體處理器

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TMS320DM8127

現行
產品規格表 立即訂購

產品詳細資料

Arm CPU 1 Arm Cortex-A8 Arm (max) (MHz) 1000 CPU 32-bit Display type 2 LCD Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 2 Hardware accelerators Face Detect Rating Catalog Power supply solution TPS65050 Operating temperature range (°C) -40 to 90
Arm CPU 1 Arm Cortex-A8 Arm (max) (MHz) 1000 CPU 32-bit Display type 2 LCD Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 2 Hardware accelerators Face Detect Rating Catalog Power supply solution TPS65050 Operating temperature range (°C) -40 to 90
FCBGA (CYE) 684 529 mm² 23 x 23
  • High-Performance DaVinci Video Processors
    • Up to 1-GHz ARM® Cortex®-A8 RISC Core
    • Up to 750-MHz C674x VLIW DSP
    • Up to 6000 MIPS and 4500 MFLOPS
    • Fully Software-Compatible with C67x+, C64x+
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • Neon™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache
    • 64KB of RAM, 48KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
  • 128KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
    • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect Engine (FD)
    • Hardware Face Detection for up to 35 Faces at OPP100
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
  • Media Controller
    • Controls the HDVPSS and ISS
  • Endianness
    • ARM and DSP Instructions/Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • One 165-MHz HD Video Capture Input
      • One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output
    • Composite or S-Video Analog Output
    • Macrovision® Support Available
    • Digital HDMI 1.3 Transmitter With Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, Rate Conversion
    • Three Graphics Layers and Compositors
  • Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1066
    • Up to Eight x 8 Devices Total 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Independent QDMA Channels
  • Dual Port Ethernet (10/100/1000 Mbps) With Optional Switch
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports With Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts, or OTG
    • Supports End Points 0–15
  • One PCI Express 2.0 Port With Integrated PHY
    • Single Port With One Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Six Configurable UART/IrDA/CIR Modules
    • UART0 With Modem Control Signals
    • Supports up to 3.6864 Mbps UART0/1/2
    • Supports up to 12 Mbps UART3/4/5
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to
    48 MHz)
    • Each With Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to
    48 MHz)
    • Three Supporting up to 1-, 4-, or 8-Bit Modes
  • Four Inter-Integrated Circuit (I2C Bus) Ports
  • Six Multichannel Audio Serial Ports (McASPs)
    • Dual Ten Serializer Transmit and Receive Ports
    • Quad Four Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 128 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Three Operating Points (OPP100, OPP120, OPP166) per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer (ETB) and
    5-Pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 684-Pin Pb-Free BGA Package (CYE Suffix), 0.8-mm Ball Pitch With Via Channel Technology to Reduce PCB Cost
  • 45-nm CMOS Technology

    •  
  • High-Performance DaVinci Video Processors
    • Up to 1-GHz ARM® Cortex®-A8 RISC Core
    • Up to 750-MHz C674x VLIW DSP
    • Up to 6000 MIPS and 4500 MFLOPS
    • Fully Software-Compatible with C67x+, C64x+
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • Neon™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache
    • 64KB of RAM, 48KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
  • 128KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
    • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect Engine (FD)
    • Hardware Face Detection for up to 35 Faces at OPP100
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
  • Media Controller
    • Controls the HDVPSS and ISS
  • Endianness
    • ARM and DSP Instructions/Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • One 165-MHz HD Video Capture Input
      • One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output
    • Composite or S-Video Analog Output
    • Macrovision® Support Available
    • Digital HDMI 1.3 Transmitter With Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, Rate Conversion
    • Three Graphics Layers and Compositors
  • Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1066
    • Up to Eight x 8 Devices Total 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Independent QDMA Channels
  • Dual Port Ethernet (10/100/1000 Mbps) With Optional Switch
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports With Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts, or OTG
    • Supports End Points 0–15
  • One PCI Express 2.0 Port With Integrated PHY
    • Single Port With One Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Six Configurable UART/IrDA/CIR Modules
    • UART0 With Modem Control Signals
    • Supports up to 3.6864 Mbps UART0/1/2
    • Supports up to 12 Mbps UART3/4/5
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to
    48 MHz)
    • Each With Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to
    48 MHz)
    • Three Supporting up to 1-, 4-, or 8-Bit Modes
  • Four Inter-Integrated Circuit (I2C Bus) Ports
  • Six Multichannel Audio Serial Ports (McASPs)
    • Dual Ten Serializer Transmit and Receive Ports
    • Quad Four Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 128 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Three Operating Points (OPP100, OPP120, OPP166) per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer (ETB) and
    5-Pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 684-Pin Pb-Free BGA Package (CYE Suffix), 0.8-mm Ball Pitch With Via Channel Technology to Reduce PCB Cost
  • 45-nm CMOS Technology

    •  

TMS320DM8127 DaVinci Digital Media processors are highly integrated, programmable platforms that leverage the technology to meet the processing needs of the following applications to name a few:IP Network Cameras Industrial Automation Network Cameras Stereo Cameras Video Surveillance HD Video Conferencing Car Black BoxHome Audio and Video Equipment

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailbox

The TMS320DM8127 DaVinci Digital Media processors also include a high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci Digital Media processors have a complete set of development tools for both the ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows™ debugger interface for visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip

TMS320DM8127 DaVinci Digital Media processors are highly integrated, programmable platforms that leverage the technology to meet the processing needs of the following applications to name a few:IP Network Cameras Industrial Automation Network Cameras Stereo Cameras Video Surveillance HD Video Conferencing Car Black BoxHome Audio and Video Equipment

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailbox

The TMS320DM8127 DaVinci Digital Media processors also include a high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci Digital Media processors have a complete set of development tools for both the ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows™ debugger interface for visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip
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類型 標題 日期
* Data sheet TMS320DM8127 DaVinci™ Video Processors datasheet (Rev. C) 2014年 3月 25日
* Errata TMS320DM8127 DaVinci™ Video Processors Errata (Silicon Revs 3.0, 2.1) (Rev. C) 2014年 3月 25日
* User guide TMS320DM8127 and TMS320DM814x DaVinci™ Digital Media Processors TRM (Rev. G) 2016年 6月 30日
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
More literature TMDSCSK8127 Quick Start Guide 2017年 1月 5日
White paper Low-latency design considerations for video-enabled aerial drones 2016年 9月 15日
User guide DM38x and TMS320DM8127 DaVinci™ Face Detect User's Guide (Rev. A) 2016年 6月 30日
User guide DM38x and TMS320DM8127 DaVinci™ Imaging Subsystem (ISS) User's Guide (Rev. A) 2016年 6月 30日
Application note Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A) 2013年 7月 19日
More literature DM81x Design Network Partners 2012年 6月 5日
Application note TI814x-DDR3-Init-U-Boot 2011年 10月 31日
Application note Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
Product overview DaVinci DM8168 and DM8148 Product Bulletin 2011年 3月 1日
Product overview Software Makes Development Easy for DM8168 and DM8148 2011年 3月 1日
Product overview Video Analytics on TI's Davinci Digital Media Processors Backgrounder 2011年 3月 1日
White paper C6Accel Whitepaper 2010年 9月 22日
User guide TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) 2010年 7月 30日
Application note Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB 2009年 11月 25日

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開發板

Z3-3P-VIDEO-EVMS — Z3 技術處理器視訊評估模組

Z3 develops and supports open-source software architectures focused on TI's DaVinci and AM57x processors. Products include multimedia centric framework, peripheral drivers, production modules and complete product design services. Z3 also provides system level design and integration for both wired (...)
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TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比，XDS200 是兼具低成本與優異效能的完美平衡，可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

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TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

LINUXEZSDK-DAVINCI — Linux EZ Software Development Kit (EZSDK) for DM814x and DM816x - ALPHA

The Linux EZ Software Development Kit (EZ SDK) allows customers to evaluate their devices in minutes and begin development in less than an hour. This kit provides everything DaVinci™ developers need to evaluate and start developing on the DaVinci™ DM816x/DM814x processors. With the (...)

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Arm 式處理器
TMS320DM8127 — DaVinci 數位媒體處理器 TMS320DM8147 — DaVinci 數位媒體處理器 TMS320DM8148 — DaVinci 數位媒體處理器
數位訊號處理器 (DSP)
TMS320DM8165 — DaVinci 數位媒體處理器 TMS320DM8167 — DaVinci 數位媒體處理器 TMS320DM8168 — DaVinci 數位媒體處理器
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驅動程式或資料庫

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
OMAPL137-HT — 高溫低功耗 C674x 浮點 DSP + Arm 處理器 - 高達 456 MHz OMAPL138B-EP — 強化產品低功耗 C674x 浮點 DSP + Arm9 處理器 -345 MHz TMS320DM8127 — DaVinci 數位媒體處理器
數位訊號處理器 (DSP)
SM320C6201-EP — 增強型產品 C6201 定點 DSP SM320C6415-EP — 強化型產品 C6415 定點 DSP SM320C6424-EP — 強化型產品 C6424 定點 DSP SM320C6455-EP — 強化型產品 C6455 定點 DSP SM320C6472-HIREL — 高可靠性產品 6 核心 C6472 定點 DSP SM320C6678-HIREL — 高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP SM320C6701 — 軍用應用的單核 C67x 浮點 DSP - 高達 167MHz SM320C6701-EP — 增強型產品 C6701 浮點 DSP SM320C6711D-EP — 增強型產品 C6711D 浮點 DSP SM320C6712D-EP — 增強型產品 C6712D DSP SM320C6713B-EP — 強化型產品 C6713 浮點 DSP SM320C6727B — 軍用級 C6727B 浮點 DSP SM320C6727B-EP — 強化型產品 C6727 浮點 DSP SMJ320C6201B — 軍用定點數位訊號處理器 SMJ320C6203 — 軍用級 C62x 定點 DSP - 陶瓷封裝 SMJ320C6701 — 軍用級 C67x 浮點 DSP - 陶瓷封裝 SMJ320C6701-SP — 航太級 C6701 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 SMV320C6727B-SP — 航太級 C6727B 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 TMS320C6202B — C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B — C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 — 定點數位訊號處理器 TMS320C6205 — 定點數位訊號處理器 TMS320C6211B — C62x 定點 DSP - 高達 167MHz TMS320C6421Q — C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424Q — C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6452 — C64x+ 定點 DSP - 高達 900MHz、1Gbps 乙太網路 TMS320C6454 — C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6455 — C64x+ 定點 DSP 最高 1.2GHz、64 位元 EMIFA、32 與 16 位元 DDR2、1Gbps 乙太網路 TMS320C6457 — 通訊基礎設施數位訊號處理器 TMS320C6701 — C67x 浮點 DSP - 高達 167MHz、McBSP TMS320C6711D — C67x 浮點 DSP - 高達 250MHz、McBSP、32 位元 EMIFA TMS320C6712D — C67x 浮點 DSP - 高達 150MHz、McBSP、16 位元 EMIFA TMS320C6720 — C67x 浮點 DSP - 200MHz、McASP、16 位元 EMIFA TMS320C6722B — C67x 浮點 DSP - 高達 250MHz、McASP、16 位元 EMIFA TMS320C6726B — C67x 浮點 DSP - 高達 266MHz、McASP、16 位元 EMIFA TMS320C6727 — C67x 浮點 DSP - 高達 250MHz、McASP、32 位元 EMIFA TMS320C6727B — C67x 浮點 DSP - 高達 350MHz、McASP、32 位元 EMIFA TMS320C6743 — 低功耗 C674x 浮點 DSP- 375MHz TMS320C6745 — 低功耗 C674x 浮點 DSP- 456MHz，QFP TMS320C6747 — 低功耗 C674x 浮點 DSP- 456MHz，PBGA
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驅動程式或資料庫

C67X-DSPLIB — Download TMS320C67x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

支援產品和硬體

支援產品和硬體

產品
Arm 式處理器
OMAPL137-HT — 高溫低功耗 C674x 浮點 DSP + Arm 處理器 - 高達 456 MHz OMAPL138B-EP — 強化產品低功耗 C674x 浮點 DSP + Arm9 處理器 -345 MHz TMS320DM8127 — DaVinci 數位媒體處理器
數位訊號處理器 (DSP)
SM320C6201-EP — 增強型產品 C6201 定點 DSP SM320C6415-EP — 強化型產品 C6415 定點 DSP SM320C6424-EP — 強化型產品 C6424 定點 DSP SM320C6455-EP — 強化型產品 C6455 定點 DSP SM320C6472-HIREL — 高可靠性產品 6 核心 C6472 定點 DSP SM320C6678-HIREL — 高可靠性產品高效能 8 核心 C6678 定點和浮點 DSP SM320C6701 — 軍用應用的單核 C67x 浮點 DSP - 高達 167MHz SM320C6701-EP — 增強型產品 C6701 浮點 DSP SM320C6711D-EP — 增強型產品 C6711D 浮點 DSP SM320C6712D-EP — 增強型產品 C6712D DSP SM320C6713B-EP — 強化型產品 C6713 浮點 DSP SM320C6727B — 軍用級 C6727B 浮點 DSP SM320C6727B-EP — 強化型產品 C6727 浮點 DSP SMJ320C6201B — 軍用定點數位訊號處理器 SMJ320C6203 — 軍用級 C62x 定點 DSP - 陶瓷封裝 SMJ320C6701 — 軍用級 C67x 浮點 DSP - 陶瓷封裝 SMJ320C6701-SP — 航太級 C6701 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 SMV320C6727B-SP — 航太級 C6727B 浮點 DSP - 具陶瓷封裝的抗輻射 V 類 TMS320C6202B — C62x 定點 DSP - 高達 300MHz、384KB TMS320C6203B — C62x 定點 DSP - 高達 300MHz、896KB TMS320C6204 — 定點數位訊號處理器 TMS320C6205 — 定點數位訊號處理器 TMS320C6211B — C62x 定點 DSP - 高達 167MHz TMS320C6421Q — C64x+ 定點 DSP - 最高 600MHz、8 位元 EMIFA、16 位元 DDR2 TMS320C6424Q — C64x+ 定點 DSP - 最高 600MHz、16/8 位元 EMIFA、32/16 位元 DDR2 TMS320C6452 — C64x+ 定點 DSP - 高達 900MHz、1Gbps 乙太網路 TMS320C6454 — C64x+ 定點 DSP - 高達 1GHz、64 位元 EMIFA、32/16 位元 DDR2、1 Gbps 乙太網路 TMS320C6455 — C64x+ 定點 DSP 最高 1.2GHz、64 位元 EMIFA、32 與 16 位元 DDR2、1Gbps 乙太網路 TMS320C6457 — 通訊基礎設施數位訊號處理器 TMS320C6701 — C67x 浮點 DSP - 高達 167MHz、McBSP TMS320C6711D — C67x 浮點 DSP - 高達 250MHz、McBSP、32 位元 EMIFA TMS320C6712D — C67x 浮點 DSP - 高達 150MHz、McBSP、16 位元 EMIFA TMS320C6720 — C67x 浮點 DSP - 200MHz、McASP、16 位元 EMIFA TMS320C6722B — C67x 浮點 DSP - 高達 250MHz、McASP、16 位元 EMIFA TMS320C6726B — C67x 浮點 DSP - 高達 266MHz、McASP、16 位元 EMIFA TMS320C6727 — C67x 浮點 DSP - 高達 250MHz、McASP、32 位元 EMIFA TMS320C6727B — C67x 浮點 DSP - 高達 350MHz、McASP、32 位元 EMIFA TMS320C6743 — 低功耗 C674x 浮點 DSP- 375MHz TMS320C6745 — 低功耗 C674x 浮點 DSP- 456MHz，QFP TMS320C6747 — 低功耗 C674x 浮點 DSP- 456MHz，PBGA
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驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
使用指南: PDF
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

支援產品和硬體

支援產品和硬體

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檢查產品詳細資料頁面以確認支援。
啟動 下載選項
模擬型號

DM814x, DM8127 CYE BSDL Model (Rev. A)

SPRM550A.ZIP (16 KB) - BSDL Model
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模擬型號

DM814x, DM8127 CYE IBIS Model, Revision 2.01 (Rev. A)

SPRM555A.ZIP (3890 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (CYE) 684 Ultra Librarian
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