產品詳細資料

Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 2.1 CON (typ) (pF) 150 ON-state leakage current (max) (µA) 0.029 Supply current (typ) (µA) 25 Bandwidth (MHz) 40 Operating temperature range (°C) -55 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic Input/output continuous current (max) (mA) 330 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -22
Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 2.1 CON (typ) (pF) 150 ON-state leakage current (max) (µA) 0.029 Supply current (typ) (µA) 25 Bandwidth (MHz) 40 Operating temperature range (°C) -55 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic Input/output continuous current (max) (mA) 330 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -22
VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • –55°C to +125°C operating temperature
  • Low on-resistance: 2.1 Ω
  • Low charge injection: -10 pC
  • High current support: 330 mA (maximum)
  • Latch-up immune
  • 1.8 V logic compatible
  • Integrated pull-up and pull-down resistor on logic pins
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • –55°C to +125°C operating temperature
  • Low on-resistance: 2.1 Ω
  • Low charge injection: -10 pC
  • High current support: 330 mA (maximum)
  • Latch-up immune
  • 1.8 V logic compatible
  • Integrated pull-up and pull-down resistor on logic pins
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching

The TMUX7219M is a complementary metal-oxide semiconductor (CMOS) switch with latch-up immunity in a single channel, 2:1 (SPDT) configuration. The device works with a single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7219M supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

The TMUX7219M can be enabled or disabled by controlling the EN pin. When disabled, both signal path switches are off. When enabled, the SEL pin can be used to turn on signal path 1 (S1 to D) or signal path 2 (S2 to D). All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments. Additionally, the TMUX7219M is rated for extended temperature use down to –55°C, making it ideal for harsh industrial and aerospace applications.

The TMUX7219M is a complementary metal-oxide semiconductor (CMOS) switch with latch-up immunity in a single channel, 2:1 (SPDT) configuration. The device works with a single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7219M supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

The TMUX7219M can be enabled or disabled by controlling the EN pin. When disabled, both signal path switches are off. When enabled, the SEL pin can be used to turn on signal path 1 (S1 to D) or signal path 2 (S2 to D). All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments. Additionally, the TMUX7219M is rated for extended temperature use down to –55°C, making it ideal for harsh industrial and aerospace applications.

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* Data sheet TMUX7219M 44-V, Latch-Up Immune, Extended Temperature, 2:1 (SPDT) Precision Switch with 1.8-V Logic datasheet PDF | HTML 2022年 5月 9日

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開發板

TMUX72XXDGKEVM — TMUX72xx DGK 封裝評估模組

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使用指南: PDF
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介面轉接器

LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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模擬型號

TMUX7219 IBIS model (Rev. B) (Rev. B)

SCDM249B.ZIP (263 KB) - IBIS Model
模擬型號

TMUX7219 PSpice Model

SCDM261.ZIP (113 KB) - PSpice Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VSSOP (DGK) 8 Ultra Librarian

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