首頁 介面 二極體 ESD 防護二極體
首頁
介面
二極體
ESD 防護二極體

TPD2E007

現行

適用 AC 訊號資料介面的雙 10-pF、±13-V、±8-kV ESD 防護二極體

立即訂購
產品規格表

TPD2E007

現行
產品規格表 立即訂購

產品詳細資料

Package name LGA (PicoStar), SOT-SC70 Peak pulse power (8/20 μs) (max) (W) 0.27 Vrwm (V) 13 Bi-/uni-directional Bi-directional Number of channels 2 IO capacitance (typ) (pF) 10 IEC 61000-4-2 contact (±V) 8000 IEC 61000-4-5 (A) 4.5 Clamping voltage (V) 20 Dynamic resistance (typ) 3.5 Interface type Audio Breakdown voltage (min) (V) 14 IO leakage current (max) (nA) 50 Rating Catalog Operating temperature range (°C) -40 to 85
Package name LGA (PicoStar), SOT-SC70 Peak pulse power (8/20 μs) (max) (W) 0.27 Vrwm (V) 13 Bi-/uni-directional Bi-directional Number of channels 2 IO capacitance (typ) (pF) 10 IEC 61000-4-2 contact (±V) 8000 IEC 61000-4-5 (A) 4.5 Clamping voltage (V) 20 Dynamic resistance (typ) 3.5 Interface type Audio Breakdown voltage (min) (V) 14 IO leakage current (max) (nA) 50 Rating Catalog Operating temperature range (°C) -40 to 85
PICOSTAR (YFM) 4 0.5929 mm² 0.77 x 0.77 SOT-SC70 (DCK) 3 4.2 mm² 2 x 2.1
  • IEC 61000-4-2 Level 4 ESD Protection
    • ±8-kV IEC 61000-4-2 Contact Discharge
    • ±15-kV IEC 61000-4-2 Air-Gap Discharge
  • IEC 61000-4-5 Surge Protection
    • 4.5-A Peak Pulse Current (8/20-µs Pulse)
  • IO Capacitance 15 pF (Max)
  • Low 50-nA Leakage Current
  • Space-Saving PicoStar™ and SOT Package
  • IEC 61000-4-2 Level 4 ESD Protection
    • ±8-kV IEC 61000-4-2 Contact Discharge
    • ±15-kV IEC 61000-4-2 Air-Gap Discharge
  • IEC 61000-4-5 Surge Protection
    • 4.5-A Peak Pulse Current (8/20-µs Pulse)
  • IO Capacitance 15 pF (Max)
  • Low 50-nA Leakage Current
  • Space-Saving PicoStar™ and SOT Package

This device is a transient voltage suppressor (TVS) based electrostatic discharge (ESD) protection device designed to offer system level ESD solutions for wide range of portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data transmission (audio interface, LVDS, RS-485, RS-232, and so forth) without compromising signal integrity. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system level ESD protection for the internal ICs when placed near the connector.

The TPD2E007 is offered in a 4-bump PicoStar and 3-pin SOT (DGK) packages. The PicoStar package (YFM), with only 0.15 mm (Max) package height, is recommended for ultra space saving application where the package height is a key concern. The PicoStar package can be used in either embedded PCB board applications or in surface mount applications. The industry standard SOT package offers straightforward board layout option in legacy designs.

This device is a transient voltage suppressor (TVS) based electrostatic discharge (ESD) protection device designed to offer system level ESD solutions for wide range of portable and industrial applications. The back-to-back diode array allows AC-coupled or negative-going data transmission (audio interface, LVDS, RS-485, RS-232, and so forth) without compromising signal integrity. This device exceeds the IEC 61000-4-2 (Level 4) ESD protection and is ideal for providing system level ESD protection for the internal ICs when placed near the connector.

The TPD2E007 is offered in a 4-bump PicoStar and 3-pin SOT (DGK) packages. The PicoStar package (YFM), with only 0.15 mm (Max) package height, is recommended for ultra space saving application where the package height is a key concern. The PicoStar package can be used in either embedded PCB board applications or in surface mount applications. The industry standard SOT package offers straightforward board layout option in legacy designs.
filter 尋找其它 ESD 防護二極體
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 5
類型 標題 日期
* Data sheet TPD2E007 2-Channel ESD Protection Array for AC-Coupled/Negative-Rail Data Interfaces datasheet (Rev. I) PDF | HTML 2016年 3月 22日
Selection guide System-Level ESD Protection Guide (Rev. D) 2022年 9月 7日
Application note ESD Packaging and Layout Guide (Rev. B) PDF | HTML 2022年 8月 18日
White paper Designing USB for short-to-battery tolerance in automotive environments 2016年 2月 10日
Analog Design Journal Design Considerations for System-Level ESD Circuit Protection 2012年 9月 25日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ESDEVM — ESD 評估模組

靜電敏感裝置 (ESD) 評估模組 (EVM) 是我們大多數 ESD 產品組合的開發平台。此電路板配備所有傳統 ESD 元件封裝，可測試任意數量的裝置。裝置可以焊接到其相應的元件封裝上，然後進行測試。對於一般高速 ESD 二極體，會實作阻抗控制的配置以取得 S 參數並取消內嵌電路板軌跡。對於非高速 ESD 二極體，其元件封裝會包含連接至測試點的軌跡，讓您輕鬆執行 DC 測試，例如崩潰電壓、保持電壓、洩漏等。電路板配置也可以透過將訊號針腳短路到訊號所在的任何地方，讓任何裝置針腳都能輕鬆地連接到電源 (VCC) 或接地。
使用指南: PDF | HTML
TI.com 無法提供
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
View Options

許多 TI 參考設計包含 TPD2E007

使用我們的參考設計選擇工具，以檢視並找出最適合您的應用和參數的設計。

檢視參考設計
封裝 針腳 CAD 符號、佔位空間與 3D 模型
PICOSTAR (YFM) 4 Ultra Librarian
SOT-SC70 (DCK) 3 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片