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TS3DDR3812

現行

適用 DDR3 應用的 3.3-V、2:1 (SPDT) 12 通道開關

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產品規格表

TS3DDR3812

現行
產品規格表 立即訂購

產品詳細資料

Protocols DDR3 Configuration 2:1 SPDT Number of channels 12 Bandwidth (MHz) 1675 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 3 Ron (typ) (mΩ) 8000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Supply current (typ) (µA) 300 ESD HBM (typ) (kV) 2 Operating temperature range (°C) -40 to 85 Crosstalk (dB) -71 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5.6 CON (typ) (pF) 2 Off isolation (typ) (dB) -42 OFF-state leakage current (max) (µA) 1 Propagation delay time (µs) 0.00004 Ron (max) (mΩ) 12000 Ron channel match (max) (Ω) 1 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 5 Turnon time (enable) (max) (ns) 7 VIH (min) (V) 2 VIL (max) (V) 0.8
Protocols DDR3 Configuration 2:1 SPDT Number of channels 12 Bandwidth (MHz) 1675 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 3 Ron (typ) (mΩ) 8000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Supply current (typ) (µA) 300 ESD HBM (typ) (kV) 2 Operating temperature range (°C) -40 to 85 Crosstalk (dB) -71 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5.6 CON (typ) (pF) 2 Off isolation (typ) (dB) -42 OFF-state leakage current (max) (µA) 1 Propagation delay time (µs) 0.00004 Ron (max) (mΩ) 12000 Ron channel match (max) (Ω) 1 RON flatness (typ) (Ω) 1.5 Turnoff time (disable) (max) (ns) 5 Turnon time (enable) (max) (ns) 7 VIH (min) (V) 2 VIL (max) (V) 0.8
WQFN (RUA) 42 31.5 mm² 9 x 3.5
  • Compatible with DDR3 SDRAM Standard (JESD79-3D)
  • Wide Bandwidth of 1.675 GHz
  • Low Propagation Delay (tpd = 40 ps Typ)
  • Low Bit-to-Bit Skew (tsk(o) = 6 ps Typ)
  • Low and Flat ON-State Resistance
    (rON = 8 Ω Typ)
  • Low Input/Output Capacitance
    (CON = 5.6 pF Typ)
  • Low Crosstalk (XTALK = –43 dB,
    Typ at 250 MHz)
  • VCC Operating Range from 3 V to 3.6 V
  • Rail-to-Rail Switching on Data I/O Ports
    (0 to VCC)
  • Separate Switch Control Logic for Upper and Lower 6-Channels
  • Dedicated Enable Logic Supports Hi-Z Mode
  • IOFF Protection Prevents Current Leakage in Powered Down State (VCC = 0 V)
  • ESD Performance Tested Per JESD22
    • 2000 V Human Body Model
      (A114B, Class II)
    • 1000 V Charged Device Model (C101)
  • 42-pin RUA Package (9 × 3.5 mm, 0.5 mm Pitch)
  • Compatible with DDR3 SDRAM Standard (JESD79-3D)
  • Wide Bandwidth of 1.675 GHz
  • Low Propagation Delay (tpd = 40 ps Typ)
  • Low Bit-to-Bit Skew (tsk(o) = 6 ps Typ)
  • Low and Flat ON-State Resistance
    (rON = 8 Ω Typ)
  • Low Input/Output Capacitance
    (CON = 5.6 pF Typ)
  • Low Crosstalk (XTALK = –43 dB,
    Typ at 250 MHz)
  • VCC Operating Range from 3 V to 3.6 V
  • Rail-to-Rail Switching on Data I/O Ports
    (0 to VCC)
  • Separate Switch Control Logic for Upper and Lower 6-Channels
  • Dedicated Enable Logic Supports Hi-Z Mode
  • IOFF Protection Prevents Current Leakage in Powered Down State (VCC = 0 V)
  • ESD Performance Tested Per JESD22
    • 2000 V Human Body Model
      (A114B, Class II)
    • 1000 V Charged Device Model (C101)
  • 42-pin RUA Package (9 × 3.5 mm, 0.5 mm Pitch)

The TS3DDR3812 is a 12-channel, 1:2 multiplexer/demultiplexer switch designed for DDR3 applications. It operates from a 3 to 3.6 V supply and offers low and flat ON-state resistance as well as low I/O capacitance which allow it to achieve a typical bandwidth of 1.675 GHz.

Channels A0 through A11 are divided into two banks of six bits and are independently controlled via two digital inputs called SEL1 and SEL2. These select inputs control the switch position of each 6-bit DDR3 source and allow them to be routed to one of two end-points. Alternatively, the switch can be used to connect a single endpoint to one of two 6-bit DDR3 sources. For switching 12-bit DDR3 sources, simply connect SEL1 and SEL2 together externally and control all 12 channels with a single GPIO input. An EN input allows the entire chip to be placed into a high-impedance (Hi-Z) state while not in use.

These characteristics make the TS3DDR3812 an excellent choice for use in memory, analog/digital video, LAN, and other high-speed signal switching applications.

The TS3DDR3812 is a 12-channel, 1:2 multiplexer/demultiplexer switch designed for DDR3 applications. It operates from a 3 to 3.6 V supply and offers low and flat ON-state resistance as well as low I/O capacitance which allow it to achieve a typical bandwidth of 1.675 GHz.

Channels A0 through A11 are divided into two banks of six bits and are independently controlled via two digital inputs called SEL1 and SEL2. These select inputs control the switch position of each 6-bit DDR3 source and allow them to be routed to one of two end-points. Alternatively, the switch can be used to connect a single endpoint to one of two 6-bit DDR3 sources. For switching 12-bit DDR3 sources, simply connect SEL1 and SEL2 together externally and control all 12 channels with a single GPIO input. An EN input allows the entire chip to be placed into a high-impedance (Hi-Z) state while not in use.

These characteristics make the TS3DDR3812 an excellent choice for use in memory, analog/digital video, LAN, and other high-speed signal switching applications.

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技術文件

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類型 標題 日期
* Data sheet 12-CHANNEL, 1:2 MUX/DEMUX SWITCH FOR DDR3 APPLICATIONS datasheet (Rev. B) 2013年 6月 3日
Application note Preventing Excess Power Consumption on Analog Switches 2008年 7月 3日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日

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開發板

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LP AM263 配備了 Sitara AM2634 處理器及其他零組件，可讓使用者使用各種裝置介面，其中包括工業乙太網路 (IE)、標準乙太網路、快速序列介面 (FSI) 及其他功能，可用於輕鬆建立原型。AM2634 支援各種 IE 協定如 EtherCAT、EtherNet/IP 和 PROFINET®。

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使用指南: PDF | HTML
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模擬型號

TS3DDR3812 HSpice Model

SCDM134.ZIP (113 KB) - HSpice Model
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模擬型號

TS3DDR3812 IBIS

SCDM135.ZIP (24 KB) - IBIS Model
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WQFN (RUA) 42 Ultra Librarian
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