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> TVP6000 NTSC/PAL
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TVP5020 NTSC/PAL Video Decoder ![]() The TVP5020 is a high quality, single chip solution that converts analog NTSC/PAL into digital component video. Its basic features include:
With its high level of integration, the TVP5020 provides several benefits to a designer concerned with improving and enhancing ability to digitize and process analog video for digital video applications. Integrated Microprocessor Architecture A unique feature of the TVP5020 is its internal microprocessor, which controls much of the analog and digital processing in the device. Phase locked loops, automatic gain control, clamping, register configuration, and other functions are controlled by firmware which is downloaded via the host interface on device power up. The firmware is factory-modifiable as tradeoffs are optimized for the unique needs of particular applications. The TVP5020 is designed to detect and lock to weak or unstable signals and automatically switch to processing characteristics for enhancing performance for more standard video signals. Line-locked Sampling and Color Subcarrier Control for TVP6000 NTSC/PAL Video Encoder Line-locked sampling on the TVP5020 ensures a fixed number of samples per horizontal video line, regardless of sync timing variations such as are common with VCR and video game outputs. In addition, the TVP5020 provides a serial control output which allows precise adjustment of color subcarrier frequency and phase on compatible downstream encoders such as the TVP6000 NTSC/PAL Video Encoder. This ensures accurate color reproduction on unstable signals. The combination of line-locked sampling and color subcarrier control eliminates the need for a costly frame buffer in system architectures which don't otherwise require it. Standardized Host Port Options for Video & VBI Data Interface The TVP5020 has five different standardized host port interface options; I2C, VMI (3 modes), and VIP. The TVP5020 VMI host port interface can function with Power PC style, Motorola style, and Intel style host processors. These standard host port options provide flexibility particularly in reading processed vertical blanking interval (VBI) data from the TVP5020. The TVP5020 has an internal FIFO to store processed VBI data which tells the host microprocessor when it has data to be read from one of the 5 host standard host port interfaces. This eliminates the need for design of external application specific Ics (ASICs) to interface the standard host processors to proprietary interfaces of some competitive video decoder devices. With the VIP interface, the TVP5020 also can provide the VBI data with the video protocol. TVP5020 Functional Block Diagram
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