Design tool
PLLATINUMSIM-SW
Texas Instruments PLLatinum Simulator Tool
PLLATINUMSIM-SW
Overview
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
Features
- Part selection based on current, cost, phase noise and package
- Filter design for passive and active filters up to fourth order
- Simulation of phase noise including PLL, fractional engine, voltage-controlled oscillator (VCO), input, dividers and loop filter
- Simulation of spurs including phase detector and fractional
- Simulation of lock time including VCO digital-calibration time
- Detailed bode-plot simulation
Downloads
Additional resources you might need
Design tool
PLLATINUMSIM-SW — PLLatinum Sim Tool
Supported products & hardware
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
RF PLLs & synthesizers
IQ demodulators
Hardware development
Evaluation board
PLLATINUMSIM-SW — PLLatinum Sim Tool
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
RF PLLs & synthesizers
IQ demodulators
Hardware development
Evaluation board
Documentation
Release Information
Added cascaded phase noise analysis
What's new
- Added cascaded phase noise analysis
Related design resources
Software development
APPLICATION SOFTWARE & FRAMEWORK
IDE, CONFIGURATION, COMPILER OR DEBUGGER
Support & training
TI E2E™ forums with technical support from TI engineers
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