EtherCAT Master on Sitara Processors: Time-Triggered Send (TTS) and Sitara Scalability
This third part of the EtherCAT Master on Sitara processors training series provides an introduction to Time-Triggered Send (TTS), and then discusses the scalability and flexibility benefits of running EtherCAT master on Sitara processors, including the AM57x, AM437x, and AM335x devices.
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Hello, everybody. In this video we will cover the third part of EtherCAT Master on Sitara Processors Training Series. In Part 3, we will briefly explain, PRU-ICSS time-triggered send or TTS, and how TTS can be used alone with EtherCAT Master for some applications which require precision time. Also, in Part 3 of the series we will look up why Sitara offers a scalable and flexible solution for EtherCAT Master.
EtherCAT Master plus Time-Triggered Send. What is TTS? The EMAC time-triggered send or TTS is used to expand classical Ethernet to meet deterministic, time-critical or safety-relevant conditions.
TTS helps to reduce transmission jitter from 10 microseconds range to 40 nanoseconds. TTS can dynamically be enabled or disabled by the host. TTS is designed to facilitate transmission of packets at predefined cyclic instants, or triggers.
How it works-- when initialized, TTS application must provide the first cycle trigger and the first cycle period. The PRU firmware then sets cyclic triggers repeatedly. And we send, cyclically, the packets provided before the trigger in a high-priority queue.
The picture shows a quick picture explanation of jitter transmission reduction on cyclic packets when TTS is used. This is achieved thanks to a Timer Interrupt sent from the PRU to ARM, which ensures cyclic packets that need to be sent are cued before the next cycle. In the picture, transmitter cycles are marked as T1, T2, T3, etc.
Time-triggered send affects the start of the EtherCAT's cyclic packets transmission cycle, shown in the picture in yellow. Some advantages of TTS when used with EtherCAT Master are the reduction in the master clock, which allows short entire EtherCAT Master cycle times.
These can be advantages is designs that don't use distributor clocking. When EtherCAT Master cycle times are very short jitter becomes a concern, especially when jitter starts to be a large percentage of the cycle time. Another advantage is the reduction of the transmitter cyclic jitter.
It's suitable for applications requiring precision sync capability on all applications with large number of slaves, and/or applications requiring frequent communication with the slaves, such as Motion Control, and safety-critical applications. Observable reduction of cycling data frames on AM57 was from 11 microseconds to 40 nanoseconds.
EtherCAT Master on Sitara-- A Scalable and Flexible Solution. TI's Sitara ARM portfolio is completely scalable for reducer applications. TI's processor SDK gives the advantage of its immigration between platforms.
EtherCAT Master can run on all of our Sitara platforms, AM335, AM437, and AM57, and on all of the interfaces, CPSW, or PRU-ICCS ports. Also, it can run on TI-RTOS, Linus or RT-Linux, using TI's processor as the case of our framework.
TI's scalability and flexibility permits to easily port and reuse EtherCAT Master on more than one Sitara portfolio. TI's Sitara platform offers the option to use EtherCAT Master with TTS. PRU-ICCS TTS is simple to use as a black box, only need to be enabled. No special programming is required.
That is also right to use EtherCAT Master on Sitara for [INAUDIBLE] Acontis and [? TI-RTOS, ?] and also as TI Designs. As TI Designs, we have two already-published designs with Acontis EC-Master for AM335 and AM57. Also, as mentioned it Training Series Part 2, EC-Master software for TI-RTOS and Linux can be done [INAUDIBLE] from Acontis web page.
On the other hand, the TI Design for CoDeSys as EtherCAT Master running in RT-Linux is in development, and will be soon published in TI.com. TI offers the option to use regular ethernet port, CPSW or GMAC, or to use PRU-ICCS for running EtherCAT Master. TI's Sitara platform offers a scalability and flexibility. EtherCAT Master can be easily ported from or to AM335, AM437, and AM57.
For second test in EtherCAT Master, please visit our TI Designs on ti.com For more information, please visit Sitara Processors overview in www.ti.com/sitara. You can also take a look over TI Designs Online Training and post questions in our E2E. Thank you.
This video is part of a series
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EtherCAT® master on Sitara™ processors
video-playlist (4 videos)