Hello, and welcome to TI Precision Labs. In this series, we are going to discuss DisplayPort interface, also known as DP. DP is a digital display interface introduced in 2008 as the next generation display interface. It is designed to replace older display standards, such as VGA and DVI, and open up new possibilities in personal computing, digital displays, and consumer electronics.

DisplayPort 2.0 will be capable of two 8K displays at 120 Hertz with 30 bpp and HDR or two 4K displays at 144 Hertz and 24 bpp with no compression. DisplayPort is also compatible with legacy display connections. With the addition of a simple adapter, a DP cable can connect a DP source to a legacy VGA, a single link DVI, or HTML display.

For any DisplayPort source transmitter and sink receiver, there are three major components-- the main link, the auxiliary or aux channel, and the Hot Plug Detect, or HPD. The main link is used for transmission of video. The main link consist of unidirectional serial data channels called lanes. The aux channel is a 1 megabit per second, half-duplex, bidirectional data channel used for control and status information. HPD is a 3.3 volt signal provided by the sink to the source.

HPD serves two purposes critical for startup of the DisplayPort communication link between source transmitter and sink receiver. First, HPD serves as a sink presence and absence notification. When HPD is high, or 3.3 volts, this indicates the presence of a sink. When HPD is low, or 0 for greater than 2 milliseconds, this indicates the absence or the removal of the sink.

Second, HPD serves as an interrupt from the sink to the source. When HPD is low, or 0 between 0.5 to 1 milliseconds, this indicates an interrupt event. A sink requests the source to read the sink's DPCD register using the aux interface and to take an appropriate action. The aux is a bidirectional, half-duplex, differential interface at 1 megabits per second data rate. Aux communication starts when a sink is plugged and carries management and device control data for the main link using VESA, EDID, and VESA MCCS standards.

In a standard DP connection, each lane has a dedicated set of twisted pair wires and transmits data across it using differential signaling. There is no dedicated clock lane with a DP connection, as the clock is embedded into the data.

DisplayPort only operates at a specific data rate. The DisplayPort 2.0 standard defines seven data rates across the main link-- 1.62 gigabits per second, or RBR; 2.7 gigabits per second, or HBR; 5.4 gigabits per second, or HBR2; 8.1 gigabits per second, or HBR3; 10 gigabits per second, or UHBR10; 13.5 gigabits per second, or UHBR13.5; and 20 gigabits per second, or UHBR20.

As the data rate increases from 1.62 gigabits per second to 8.1 gigabits per second, the DP main link starts to suffer from signal distortion due to the package and the PCB copper and dielectric losses. The result is that the main link length is decreasing as the data rate is increasing. To support longer main link length, the addition of a DP signal conditioner in the form of a redriver or a retimer needs to be taken into consideration as part of the system design.

DP uses an LVDS signaling protocol. It is an AC coupled, 100 ohm, differential signaling interface. On the source side, the transmitter, the transmitter provides both amplitude and pre-emphasized control. The transmitter must support level 0, level 1, and level 2 amplitude and pre-emphasized control, while level 3 is optional. The default signal amplitude at the source is 400 millivolts peak to peak. And the default pre-emphasis level is 0 dB.

Link training is used to compensate for the signal integrity between the DP source and the DP sink. Compensation is done by changing the DP source amplitude and pre-emphasis level as requested by the sink during the initial sink connection. It can also be re-initialized if there is a data error after the initial sink connection.

The main link, with increasing data rate from 1.62 gigabits per second to 8.1 gigabits per second, starts to suffer from signal distortion due to the increase in PCB and the packaged copper and dielectric losses. Other distortions also occur due to impedance discontinuities in the main links, such as packages, vias, and connectors. The data rate is also rising faster than the current receiver design, PCB, or package technologies can keep up with.

While using expensive PCB material is one way to reduce the loss, the PCB material will soon reach its dielectric limit and become cost prohibitive. A second solution is to shorten the main link length and therefore reduce the total loss. But this solution becomes impractical in a DP system design that does require longer main link length while also requiring to operate at a higher data rate.

The redriver or retimer placed on the main link, between the source and the connector or between the connector and the sink, can help alleviate some of this design challenge. A redriver can help improve the main link signal quality by restoring the attenuated input signal through equalization and gain adjustment. A retimer can help by recovering the attenuated input signal with a clock recovery circuit, compensate the random jitter, and retransmit the signal based on a clean clock. For more information on signal conditioners, I encourage you to watch the TI Precision Labs video named, "What Is a Signal Conditioner?"

The placement of a redriver is a critical decision in a system design. Placing the redriver either too close or too far from the source transmitter or sink receiver will negate the effectiveness of the redriver, resulting in less than optimal system performance. The placement of the redriver depends on the total insertion loss of the system before the redriver receiver equalizer.

The insertion loss comes from the PCB trace, the via, the connector, the silicon package, et cetera. If we can estimate the insertion loss at the Nyquist for PCB trace, we can then calculate whether the PCB trace length is within the redriver receiver equalizer design limitation and also have an initial estimate of the redriver's equalizer setting.

Assuming skin depth limited current in microstrip or stripline, the series resistance in the return path, and a factor of 2 increase in resistance from surface roughness and a 100 ohm impedance transmission line, we can use a model formula to give us a pretty good approximation of the insertion loss at the Nyquist frequency.

In the model formula, w is a trace width in mils. f is the Nyquist frequency. Df is the PCB dissipation factor. And Dk is the PCB dielectric constant.

Now let's do an actual calculation. Let's assume DP is running at HBR2, or 5.4 gigabits per second. And the Nyquist frequency, f, is 1/2 the data rate, or 2.7 gigahertz. With a 12-inch, 6 mil trace, the dissipation factor is 0.02, and the dielectric constant is 4.3.

Then we can calculate the estimated loss at approximately 0.53 dB per inch at 2.7 gigahertz. If we multiply 12 inches by 0.53 dB per inch, then the approximate insertion loss is 6.36 dB at 2.7 gigahertz. This is very close to the 6.54 dB at 2.7 gigahertz measured by a VNA in a real 12-inch, 6 mil trace.

If we assume a redriver can support a maximum of 12 dB loss at 2.7 gigahertz, then with an estimated loss of 0.53 dB per inch, we can assume the maximum supported distance for HBR2 will be approximately 22 inches. This estimation can also be used to configure the redriver equalization setting. If we assume the redriver is placed 10 inches from the signal source on the same board, then we can use the same estimated loss to set initial redriver equalizer to 5 dB.

Further tuning can be accomplished through the DisplayPort compliance testing. On the source transmitter side, this is accomplished by the transmitter electrical compliance test. And on the receiver sink side, this is accomplished by the receiver jitter tolerance test.

Now let's look at a real example. Before we look at the eye diagram, please review the TI Precision Labs "What is an Eye Diagram?" presentation for a basic understanding of the eye diagram. The first picture is the HBR2 5.4 gigabits per second eye diagram, directly at the output of the source transmitter. The eye is open and passing the DisplayPort eye mask requirement.

Extending the trace by 12 inches, we can now see the eye is closed and failing the DisplayPort eye mask requirement. From the calculation we did previously, we know that the approximate insertion loss is 0.53 dB per inch. For a 12-inch trace, this will be a 6.36 dB loss at 2.7 gigahertz.

If we add a redriver to the output of the 12-inch trace and set the redriver equalizer to 6 dB to match the insertion loss of the 12-inch trace, we can see the eye is open again and passing the DisplayPort eye mask requirement.

To recap what we discussed, let's go over a short quiz. Number 1, true or false-- DP is a DC coupled interface. The answer is false. Question number 2, true or false-- for a data rate of 8.1 gigabits per second and two lanes configuration, the total bandwidth is 16.2 gigabits per second. The answer is true.

Question number 3, true or false-- Hot Plug Detect is used for configuring DP lanes. The answer is false. Question number 4, true or false-- the insertion loss is the same regardless of the DP data rate. The answer is false.

Question number 5, true or false-- a DP redriver can help improve the DP main link signal quality. The answer is true. Question number 6, true or false-- the correct placement of the DP redriver is important for the design of the system. The answer is true.

In closing, I'm glad that we could offer you this segment on DisplayPort. Watch for future sessions. We'll go into more details about the standard and signal conditioning devices from Texas Instruments. Be sure to visit our TI E2E community at TI.com for questions and more information. Thanks.