PCIe layout guidelines
00:06:56
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20 DEC 2021
In this series we are going to discuss board layout recommendations for the peripheral component interconnect express or PCle. PCIe is a high-performance interconnect that enables high bandwidth, scalable, error detection, and hot-swap functionality across multiple clock boundaries. To accommodate high bandwidth and scalability, multiple traces carrying high-speed data at 16Gbps or higher are used. These high-speed lanes require special considering when designing a PCB layout.
Resources
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arrow-right Search TI's collection of signal conditioners for PCIe, SAS, and SATA products. -
arrow-right We offer an extensive portfolio of low-power, low-latency, multi-channel redrivers, redrivers and passive switches that support the PCIe®, UPI, CXL™, SAS and SATA protocols. -
arrow-right Find transceivers, SerDes and signal conditioners from Texas Instruments for more than 20 protocols -
arrow-right Download and install TINA-TI, the preferred simulator used exclusively with TI Precision Labs.
This video is part of a series
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Networking using TI Arm®-based processors
video-playlist (8 videos) -
Precision labs series: PCIe
video-playlist (5 videos)