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DRA786

ACTIVE

SoC processor w/ 2x 500 MHz C66x DSP and 2 dual Arm Cortex-M4 & EVE for audio amplifier

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Data sheet
Errata

DRA786

ACTIVE
Data sheet Order now

Product details

DSP type 2 C66x DSP (max) (MHz) 500 Operating system Android, Linux, RTOS Ethernet MAC 1000, 2-Port 1Gb switch PCIe 2 PCIe Gen2 TI functional safety category Functional Safety-Compliant Power supply solution LP873220-Q1, LP87332D-Q1, TPS65917-Q1, TPS65919-Q1 Rating Automotive Operating temperature range (°C) -40 to 125
DSP type 2 C66x DSP (max) (MHz) 500 Operating system Android, Linux, RTOS Ethernet MAC 1000, 2-Port 1Gb switch PCIe 2 PCIe Gen2 TI functional safety category Functional Safety-Compliant Power supply solution LP873220-Q1, LP87332D-Q1, TPS65917-Q1, TPS65919-Q1 Rating Automotive Operating temperature range (°C) -40 to 125
FCBGA (ABF) 367 225 mm² 15 x 15
  • Architecture designed for infotainment applications
  • Up to 2 C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512kB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Memory Interface (EMIF) module
    • Supports DDR3/DDR3L up to DDR-1066
    • Supports DDR2 up to DDR-800
    • Up to 2GB supported
  • Dual Arm® Cortex®-M4 (IPU)
  • Vision accelerationPac
    • Embedded Vision Engine (EVE)
  • Display subsystem
    • Display controller with DMA engine
    • CVIDEO / SD-DAC TV analog composite output
  • On-chip temperature sensor that is capable of generating temperature alerts
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 3-port (2 external) Gigabit Ethernet (GMAC) switch
  • Controller Area Network (DCAN) module
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol
  • Eight 32-bit general-purpose timers
  • Three configurable UART modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Two Inter-Integrated Circuit (I2C™) ports
  • Three Multichannel Audio Serial Port (McASP) modules
  • Secure Digital Input Output Interface (SDIO)
  • Up to 126 General-Purpose I/O (GPIO) pins
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
  • Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
  • 8-channel 10-bit ADC
  • PWMSS
  • Video and image processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Video input and video output
    • GPIOs when not used for video
  • Video Input Port (VIP) module
    • Support for up to 4 multiplexed input ports
  • Architecture designed for infotainment applications
  • Up to 2 C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512kB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • Memory Interface (EMIF) module
    • Supports DDR3/DDR3L up to DDR-1066
    • Supports DDR2 up to DDR-800
    • Up to 2GB supported
  • Dual Arm® Cortex®-M4 (IPU)
  • Vision accelerationPac
    • Embedded Vision Engine (EVE)
  • Display subsystem
    • Display controller with DMA engine
    • CVIDEO / SD-DAC TV analog composite output
  • On-chip temperature sensor that is capable of generating temperature alerts
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 3-port (2 external) Gigabit Ethernet (GMAC) switch
  • Controller Area Network (DCAN) module
    • CAN 2.0B protocol
  • Modular Controller Area Network (MCAN) module
    • CAN 2.0B protocol
  • Eight 32-bit general-purpose timers
  • Three configurable UART modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI interface
  • Two Inter-Integrated Circuit (I2C™) ports
  • Three Multichannel Audio Serial Port (McASP) modules
  • Secure Digital Input Output Interface (SDIO)
  • Up to 126 General-Purpose I/O (GPIO) pins
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • Automotive AEC-Q100 qualified
  • 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)
  • Five instances of Real-Time Interrupt (RTI) modules that can be used as watch dog timers
  • 8-channel 10-bit ADC
  • PWMSS
  • Video and image processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Video input and video output
    • GPIOs when not used for video
  • Video Input Port (VIP) module
    • Support for up to 4 multiplexed input ports

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8 mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (FCBGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive co-processor, hybrid radio and amplifier applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors.

Additionally, Texas Instruments (TI) provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.
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Technical documentation

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Type Title Date
* Data sheet DRA78x Infotainment Applications Processor datasheet (Rev. H) PDF | HTML 04 Feb 2020
* Errata DRA78x Silicon Errata (Rev. B) 01 Oct 2019
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 05 May 2021
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 24 Aug 2020
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06 Jan 2020
User guide DRA78x Technical Reference Manual (Rev. D) 30 Jul 2019
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 11 Jun 2019
Application note Achieving Early CAN Response on DRA7xx Devices 28 Nov 2018
Application note DRA74x_75x/DRA72x Performance (Rev. A) 31 Oct 2018
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 14 Sep 2018
Application note The Implementation of YUV422 Output for SRV 02 Aug 2018
Application note MMC DLL Tuning (Rev. B) 31 Jul 2018
Application note Integrating AUTOSAR on TI SoC: Fundamentals 18 Jun 2018
Application note ECC/EDC on TDAxx (Rev. B) 13 Jun 2018
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem 12 Jun 2018
Application note Sharing VPE Between VISIONSDK and PSDKLA 04 May 2018
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) 13 Feb 2018
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 30 Nov 2017
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 27 Nov 2017
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07 Nov 2017
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03 Nov 2017
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12 Sep 2017
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 14 Aug 2017
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 12 Jul 2017
EVM User's guide DRA78x_15X15 EVM CPU Board User's Guide 22 May 2017
EVM User's guide TDA3x_15X15 EVM CPU Board Users Guide 10 May 2017
Application note Linux Boot Time Optimizations on DRA7xx Devices 31 Mar 2017
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 17 Feb 2017
Application note Early Splash Screen on DRA7x Devices 31 Jan 2017
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15 Dec 2016
Application note Gstreamer Migration Guidelines 26 Apr 2016
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU 14 Apr 2016
Application note Tools and Techniques for Audio Debugging 13 Apr 2016
Application note Debugging Tools and Techniques With IPC3.x 30 Mar 2016
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 15 Jan 2016
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 14 Oct 2014
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13 Aug 2014
White paper Today’s high-end infotainment soon becoming mainstream 02 Jun 2014

Design & development

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