Calculation tool
TPS40040
2.25 to 5.5 V input, 300 kHz, synchronous buck controller with low pin count
Data sheet
TPS40040
- 2.25-V to 5.5-V Input
- Output Voltage from 0.6 V to 90% of VIN
- High-Side Drive for N-Channel FET
- Supports Pre-Biased Outputs
- Adaptive Anti-Cross Conduction Gate Drive
- 1%, 0.6-V Reference
- Two Fixed Switching Frequency Versions, TPS40040 (300 kHz) and TPS40041 (600 kHz)
- Three Selectable Short Circuit Protection Levels of 105 mV, 180 mV and 310 mV
- Hiccup Restart from Faults
- Voltage Mode Control
- Active Low Enable
- Thermal Shutdown Protection at 145°C
- 8-Pin, 3-mm × 3-mm SON with Ground Connection to Thermal Pad
- APPLICATIONS
- Point of Load
- Telecommunications
- DC to DC Modules
- Set Top Boxes
PowerPAD Is a trademark of Texas Instruments.
Predictive Gate Drive Is a trademark of Texas Instruments.
The TPS40040 and TPS40041 dc-to-dc controllers are designed to operate from a 2.25-V to 5.5-V input source. To reduce the number of external components, several operating parameters are fixed internally; namely, frequency, soft start time, and short circuit protection (SCP) levels. For example, the operating frequencies of TPS40040/1 are 300 kHz/600 kHz, respectively.
One of three short circuit threshold levels may be selected by the addition of an external resistor from the COMP pin to circuit ground. During power on, and before the internal soft start commands the output voltage to rise, the TPS40040/1 enters a calibration cycle, measures the current out of the COMP pin, and selects an internal SCP threshold voltage. At the end of the 1.6-ms calibration time, the output voltage is allowed to rise for a 4-ms soft start. During operation, the selected SCP threshold voltage is compared to the upper MOSFET’s voltage drop during its ON time to determine whether there is an overload condition.
The packaging of the TPS40040/1 is unique in that the PowerPAD™ is used as an electrical ground connection as well as a thermal connection.
Technical documentation
No results found. Please clear your search and try again.
View all 7 | Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Low Pin Count, Low VIN (2.5V to 5.5V Synchronous Buck DC-to-DC Controller datasheet (Rev. D) | 12 Dec 2007 | |
| Analog Design Journal | Control-Mode Quick Reference Guide (Rev. B) | PDF | HTML | 29 Aug 2023 | |
| Selection guide | Power Management Guide 2018 (Rev. R) | 25 Jun 2018 | ||
| Selection guide | DC/DC Buck Controller Solutions Selection Guide | 06 Feb 2018 | ||
| Application note | Analysis and Design of Input Filter for DC-DC Circuit | 27 Nov 2017 | ||
| EVM User's guide | Using the TPS40040-EVM-001 | 29 Jan 2007 | ||
| User guide | A 5-V Input, 1.8-V Output, 6-A Synchronous Buck Converter | 10 Apr 2006 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
TPS40040EVM-001 — 5V Input, 1.8V Output, 10A Synchronous Buck Evaluation Module
The TPS40040EVM-001 evaluation module (EVM) is a synchronous buck converter providing a fixed1.8 V output at up to 10 A from a 5 V input bus. The EVM is designed to start up from a single supply, so no additional bias voltage is required for startup. The module uses the TPS40040 (...)
User guide: PDF
Evaluation board
TPS40041EVM-001 — TPS40041 5V Input, 1.8V Output, 6A Evaluation Module
The TPS40041EVM-001 evaluation module (EVM) is a synchronous buck converter providing a fixed1.8 V output at up to 6 A from a 5 V input bus or 3 A from a 3.3 V input. The EVM is designed to start up from a single supply, so no additional bias voltage is required for (...)
User guide: PDF
Simulation model
TPS40040 TINA-TI Average Reference Design (Rev. A)
SLVJ009A.TSC (566 KB) - TINA-TI Reference Design
Simulation model
TPS40040 TINA-TI Transient Reference Design
SLVM028.TSC (753 KB) - TINA-TI Reference Design
Simulation model
TPS40040 Unencrypted PSpice Transient Model Package (Rev. A)
SLVM032A.ZIP (67 KB) - PSpice Model
Simulation model
TPS40040/1 Unencrypted PSpice Average Model Package (Rev. A)
SLVJ008A.ZIP (108 KB) - PSpice Model
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VSON (DRB) | 8 | Ultra Librarian |
Ordering & quality
Information included:
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Information included:
- Fab location
- Assembly location
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.