SBASAL3 September   2024 ADC3669

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (ADC3668 - 250 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (ADC3669 - 500 MSPS)
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics, ADC3668
    11. 5.11 Typical Characteristics, ADC3669
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Nyquist Zone Selection
        2. 7.3.1.2 Analog Front End Design
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 Multi-Chip Synchronization
        1. 7.3.3.1 SYSREF Monitor
      4. 7.3.4 Time-Stamp
      5. 7.3.5 Overrange
      6. 7.3.6 External Voltage Reference
      7. 7.3.7 Digital Gain
      8. 7.3.8 Decimation Filter
        1. 7.3.8.1 Uncommon Decimation Ratios
        2. 7.3.8.2 Decimation Filter Response
        3. 7.3.8.3 Decimation Filter Configuration
        4. 7.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 7.3.9 Digital Interface
        1. 7.3.9.1 Parallel LVDS (DDR)
        2. 7.3.9.2 Serial LVDS (SLVDS) with Decimation
        3. 7.3.9.3 Output Data Format
        4. 7.3.9.4 32-bit Output Resolution
        5. 7.3.9.5 Output MUX
        6. 7.3.9.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Digital Channel Averaging
      3. 7.4.3 Power Down Mode
    5. 7.5 Programming
      1. 7.5.1 GPIO Programming
      2. 7.5.2 Register Write
      3. 7.5.3 Register Read
      4. 7.5.4 Device Programming
      5. 7.5.5 Register Map
      6. 7.5.6 Detailed Register Description
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband Spectrum Analyzer
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Initialization Set Up
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.6 Detailed Register Description

Figure 7-74 Register 0x25
7 6 5 4 3 2 1 0
0 0 0 CFG RDY 0 0 0 0
Table 7-19 Register 0x25 Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0 Must write 0
0 CFG RDY R/W 0 This bit indicates the status of the internal fuse load after HW reset.
0: Fuse load not complete
1: Fuses are loaded, applied and device ready for programming.
3-0 0 R/W 0 Must write 0
Figure 7-75 Register 0x100
76543210
0000000RESET
Table 7-20 Register 0x100 Field Descriptions
BitFieldTypeResetDescription
7-10R/W0Must write 0
0RESETR/W0This bit resets all internal registers to the default values and self clears to 0.
Figure 7-76 Register 0x101
7 6 5 4 3 2 1 0
0 0 0 GBL PDN 0 0 0 0
Table 7-21 Register 0x101 Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
4GBL PDNR/W0Global power down. This bit powers down the entire device. This feature is also available using GPIO pins (0x146, D4-D0).
0: normal operation
1: Device in global power down mode
3-0 0 R/W 0 Must write 0
Figure 7-77 Register 0x102
7 6 5 4 3 2 1 0
0 SYSREF DET CLR 0 0 0 0 0 0
Table 7-22 Register 0x102 Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6SYSREF DET CLRR/W0This bit resets the SYSREF DET flag (0x140, D6)
0: normal operation
1: SYSREF DET flag gets reset.
5-00R/W0Must write 0
Figure 7-78 Register 0x104
7 6 5 4 3 2 1 0
0 0 0 0 0 0 CHB TERM CHA TERM
Table 7-23 Register 0x104 Field Descriptions
BitFieldTypeResetDescription
7-20R/W0Must write 0
1CHB TERMR/W0ChB internal termination. This bit sets the internal termination on channel B.
0: 100Ω differential termination
1: 200Ω differential termination
0CHA TERMR/W0ChA internal termination. This bit sets the internal termination on channel A.
0: 100Ω differential termination
1: 200Ω differential termination
Table 7-24 Register 0x10A
76543210
00000OVR CLROVR STICKY
Table 7-25 Register 0x10A Field Descriptions
BitFieldTypeResetDescription
7-30R/W0Must write 0
2-1OVR CLRR/W0This is useful for clearing the sticky bit. Setting a value of 0x2 clears the sticky OVR.
0OVR STICKYR/W0This bit makes the OVR sticky.
0: OVR is non-sticky (updated based on <OVR LENGTH>)
1: OVR is sticky (use <OVR CLR> to reset)
Table 7-26 Register 0x10B
76543210
OVR LENGTH
Table 7-27 Register 0x10B Field Descriptions
BitFieldTypeResetDescription
7-0OVR LENGTHR/W0This controls the OVR pulse expansion. This field specifies the expansion width in terms of the number of clock cycles.
For example 0x0F sets the OVR length to 16 clock cycles.
Figure 7-79 Register 0x110
76543210
LVDS TERM0LVDS HALF SWING000SWAP CH0
Table 7-28 Register 0x110 Field Descriptions
BitFieldTypeResetDescription
7LVDS TERMR/W0This bit configures the LVDS termination resistance. Setting this bit enables 100Ω termination. The default termination resistance is 50Ω
60R/W0Must write 0
5LVDS HALF SWINGR/W0This bit reduces the LVDS output swing by 50% to save power consumption.
0: Normal output swing
1: Reduced output swing
4-20R/W0Must write 0
1SWAP CHR/W1This bit internally swaps channel A and channel B.
0: Channel A and channel B are swapped
1: Normal operation
00R/W0Must write 0
Figure 7-80 Register 0x111/0x112
76543210
LVDS DATA INV [7:0]
LVDS DATA INV [15:8]
Table 7-29 Register 0x111/0x112 Field Descriptions
BitFieldTypeResetDescription
7-0LVDS DATA INV [15:0]R/W0These bits allow to invert polarity of individual LVDS output lanes as shown in Table 7-30.
0: Polarity as shown in pin diagram.
1: Polarity inverted
Table 7-30 LVDS data inversion register lane assignment
REG ADDR 0x10F 0x10E
REG BIT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
LVDS OUTPUT LANE 15 14 13 12 11 10 9 8 0 1 2 3 4 5 6 7
Figure 7-81 Register 0x113/0x114
76543210
LVDS PDN [14:8]0
0 0 0 0 0 0 0 LVDS PDN [15]
Table 7-31 Register 0x113/0x114 Field Descriptions
BitFieldTypeResetDescription
7-0LVDS PDN [15:8]R/W0These register bits power down the individual LVDS output lanes with LVDS pins into high impedance state (e.g. 0x113, D7 powers down output lane 14). The remaining LVDS lane (0-7) power down registers are in registers 0x691/0x692.
0: Normal operation
1: LVDS output lane powered down
7-00R/W0Must write 0
Figure 7-82 Register 0x115
7 6 5 4 3 2 1 0
0 0 0 0 FCLK DC FCLK DIS 0 0
Table 7-32 Register 0x115 Field Descriptions
BitFieldTypeResetDescription
7-40R/W0Must write 0
3FCLK DCR/W0This bit allows adjusting the FCLK duty cycle.
0: FCLK stays high for one DCLK cycle at the beginning of the output sample
1: FCLK stays high for 50% of the output sample
2FCLK DISR/W0This bit disables the output FCLK. FCLK is transmitted on lane DOUT0. In decimation modes where all 16 lanes are used, FCLK replaces the LSB.
0: FCLK replaces the LSB data and is transmitted on DOUT0
1: FCLK is disabled and the LSB data is transmitted on DOUT0.
10R/W0Must write 0
00R/W0Must write 0
Figure 7-83 Register 0x116
76543210
LVDS MUX ENLVDS SWAP EDGE000LVDS SCR
Table 7-33 Register 0x116 Field Descriptions
BitFieldTypeResetDescription
7LVDS MUX ENR/W0This bit enables use of the LVDS output mux in registers 0x117..0x11E.
0: LVDS output mux disabled
1: LVDS output mux enabled
6LVDS SWAP EDGER/W0This bit swaps the output data bits transmitted on rising and falling edge of DCLK.
0: Normal operation
1: Output bits on rising and falling edge are swapped.
5-30R/W0Must write 0
2-0LVDS SCRR/W0This field controls the scrambling and lsb insertion config on the output data
000: Default operation
001: Data is XOR'ed with a PRBS bit. This PRBS is inserted on the LSB position. The PRBS is generated using a large LFSR and can be treated as random for all practical scenarios
010: OVR is inserted on the LSB position
011: OVR is inserted on the LSB+1 position
100: Data is XOR'ed with a PRBS bit, and the PRBS is inserted on LSB+1 position
101: OVR is inserted on LSB+1 position, PRBS is inset on LSB position. Data is XOR'ed with PRBS
110: OVR is inserted on LSB+2 position, PRBS is inset on LSB+1 position. Data is XOR'ed with PRBS
111: Unused
Figure 7-84 Register 0x117...0x11E
76543210
DOUT1/3/5/7/9/11/13/15 MUXDOUT0/2/4/6/8/10/12/14 MUX
Table 7-34 Register 0x117...0x11E Field Descriptions
BitFieldTypeResetDescription
7-4DOUT1/3/5/7/9/11/13/15 MUXR/W0000These bits configure the data bus assignment for the individual output lanes. <LVDS MUX EN> in 0x116, D7 must be enabled.
0000: LVDS lane DOUTx carries data of internal digital bus lane DIG0
0001: LVDS lane DOUTx carries data of internal digital bus lane DIG1
...
1111: LVDS lane DOUTx carries data of internal digital bus lane DIG15
3-0DOUT0/2/4/6/8/10/12/14 MUXR/W0000
Figure 7-85 Register 0x132
7 6 5 4 3 2 1 0
HIGH FIN 0 0 0 0 0 0 0
Table 7-35 Register 0x132 Field Descriptions
Bit Field Type Reset Description
7 HIGH FIN R/W 0 This bit must be set for best AC performance for input frequencies greater than 500MHz
0: Input frequencies < 500MHz
1: Input frequencies > 500MHz
6-0 0 R/W 0 Must write 0
Figure 7-86 Register 0x140
76543210
0SYSREF DETSYSREF ORSYSREF X5SYSREF X4SYSREF X3SYSREF X2SYSREF X1
Table 7-36 Register 0x140 Field Descriptions
BitFieldTypeResetDescription
70R/W0Must write 0
6SYSREF DETR/W0This register indicates if a SYSREF signal is detected. Upon detection, this bit stays high until the bit is reset (0x102, D6) or a device reset is issued.
0: no SYSREF signal detected
1: SYSREF signal detected
5SYSREF ORR/W0This bit is the output of the five SYSREF XOR flags logically OR'ed together.
0: no SYSREF flag raised
1: one of the five SYSREF XOR flags is raised.
4-0SYSREF X5..X1R/W0These bits are the XOR flags from the SYSREF window monitoring circuitry. The sampling clock falling edge is used to capture the SYSREF signal. If a SYSREF signal transition happens within -60/+140 ps of the SYSREF capture, the appropriate XOR flag gets raised. These bits are updated on every SYSREF rising edge.
X1: SYSREF leading sample clock by 20 to 60ps
X2: SYSREF leading sample clock by 20ps to 0ps or SYSREF lagging sample clock by 0 to 20ps
X3: SYSREF lagging sample clock by up to 20 to 60ps
X4: SYSREF lagging sample clock by 60 to 100ps
X5: SYSREF lagging sample clock by 100 to 140ps
0: No SYSREF transition detected
1: SYSREF transition detected within given window
Figure 7-87 Register 0x146
76543210
000GPIO CONFIG
Table 7-37 Register 0x146 Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
4-0GPIO CONFIGR/W0These register bits configure the functionality of the two GPIO pins as shown in Table 7-38.
Table 7-38 GPIO pin configuration
GPIO CONFIGGPIO1GPIO0
00000NOT USEDSYSREF
00011GLOBAL POWER DOWNSYSREF
00100EXTERNAL REFERENCESYSREF
00101NCO SWITCH1NCO SWITCH0
01000NOT USEDSYSREF
01001OVR CHB/CHASYSREF
01010NOT USEDGLOBAL POWER DOWN
01011OVR CHB/CHAGLOBAL POWER DOWN
10010OVR CHBOVR CHA
all othersNOT USED
Figure 7-88 Register 0x14A
76543210
0 00PATTERN CLK0TEST PATTERN
Table 7-39 Register 0x14A Field Descriptions
BitFieldTypeResetDescription
7-50R/W

Must write 0

4PATTERN CLKR/W0This controls the clock of the pattern signal generator. Setting this bit switches the pattern generator clock to decimation clock.
0: Pattern clock uses the ADC sampling clock
1: Pattern clock uses the DDC clock.
30R/W0Must write 0
2-0TEST PATTERNR/W0This field controls the type of pattern injected. Default value is 0 and indicates that the pattern generator is off. The generated pattern is 20 bit wide. In 16 bit resolution mode, MSB 16 bits of the pattern mode are sent out. In 32 bit resolution mode, 12 zero bits are padded to the generated pattern and sent out.
000: Test pattern is disabled
001: Ramp pattern with a step of 1 (at 20 bit level, which is equivalent to 1/16 at 16 bit level)
010: Ramp pattern with a step value set by CUSTOM PATTERN. For example, to configure a ramp pattern with unit step in 16 bit mode, the CUSTOM PATTERN must be set to 0x010
011: Unused
100: Static pattern set by CUSTOM PATTERN
101: Pattern toggles between CUSTOM PATTERN and invert of CUSTOM PATTERN
110: Pattern toggles between CUSTOM PATTERN and 0
111: Unused
Figure 7-89 Register 0x14B/0x14C/0x14D
76543210
CUSTOM PATTERN [7:0]
CUSTOM PATTERN [15:8]
0000CUSTOM PATTERN [19:16]
Table 7-40 Register 0x14B/0x14C/0x14D Field Descriptions
BitFieldTypeResetDescription
7-0CUSTOM PATTERN [19:0]R/W0This filed controls the pattern generator. This controls different functions depending on the TEST PATTERN setting
Figure 7-90 Register 0x15B
76543210
DIGITAL GAIN CHA [7:0]
Table 7-41 Register 0x15B Field Descriptions
BitFieldTypeResetDescription
7-0DIGITAL GAIN CHA [7:0]R/W0This register controls digital gain for channel A and is interpreted as a 2's complement number. Maximum gain is 6dB (20 x log (1+(DIGITAL GAIN CHA / 128))).
Figure 7-91 Register 0x15C
76543210
DIGITAL GAIN CHB [7:0]
Table 7-42 Register 0x15C Field Descriptions
BitFieldTypeResetDescription
7-0DIGITAL GAIN CHB [7:0]R/W0This register controls digital gain for channel B and is interpreted as a 2's complement number. Maximum gain is 6dB (20 x log (1+(DIGITAL GAIN CHB / 128))).
Figure 7-92 Register 0x160
76543210
00000

0

SYSREF MODE
Table 7-43 Register 0x160 Field Descriptions
BitFieldTypeResetDescription
7-20R/W0Must write 0
1-0SYSREF MODER/W0This controls the global SYSREF mask including the test pattern.
00: Pass all SYSREF pulses
01: Pass the first SYSREF pulse and gates subsequent pulses
10: Gate all SYSREF pulses
11: Issue new SYSREF pulse. The pulse is issued when the state transitions to 11
Figure 7-93 Register 0x161
76543210
LVDS SYSREF MASKDDC SYSREF MASKNCO SYSREF MASKTIMER SYSREF MASK
Table 7-44 Register 0x161 Field Descriptions
BitFieldTypeResetDescription
7-6LVDS SYSREF MASKR/W0This controls the SYSREF pulse going to the SLVDS block (decimation only). Default setting is 0 and passes all SYSREF pulses.
00: Pass all SYSREF pulses
01: Pass the first SYSREF pulse and gates subsequent pulses
10: Gate all SYSREF pulses
11: Issue new SYSREF pulse. The pulse is issued when the state transitions to 11
5-4DDC SYSREF MASKR/W0This controls the SYSREF pulse of DDC block. The value - function map is same as LVDS SYSREF MASK
3-2NCO SYSREF MASKR/W0This controls the SYSREF pulse of NCO block. The value - function map is same as LVDS SYSREF MASK
1-0TIMER SYSREF MASKR/W0This controls the SYSREF pulse of TIMER block of the NCO. The value - function map is same as LVDS SYSREF MASK
Figure 7-94 Register 0x162
76543210
SYSREF TIME STAMP06dB GAIN OVERRIDECOMPLEX DDC ENOUTPUT RESOUTPUT FORMAT
Table 7-45 Register 0x162 Field Descriptions
BitFieldTypeResetDescription
7-6SYSREF TIME STAMPR/W0Setting this field to 0x3 allows the SYSREF input to replace the LSB. OVR_ON_LSB setting takes precedence.
50R/W0Must write 0
4-36dB GAIN OVERRIDER/W0This field controls 6dB gain setting of the DDC. The 6dB gain is applied in COMPLEX DDC mode by default. Setting this to 0x3 forces 6dB gain on the DDC output, irrespective of the DDC mode. Setting this to 0x2 forces unity gain irrespective of the DDC mode.
2COMPLEX DDC ENR/W0This bit enables complex decimation for all DDCs. The decimation factor is set in 0x167..0x169
0: Real decimation
1: Complex decimation
1OUTPUT RESR/W0This bit increases the output resolution from 16-bit to 32-bit
0: 16-bit output resolution
1: 32-bit output resolution
0OUTPUT FORMATR/W0This bit selects the output format
0: Output format is 2s complement
1: Output format is offset binary
Figure 7-95 Register 0x163
76543210
DDC3 MUXDDC2 MUXDDC1 MUXDDC0 MUX
Table 7-46 Register 0x163 Field Descriptions
BitFieldTypeResetDescription
7-6DDC3 MUXR/W0These register bits set the input data source to the individual decimation filters.
00: Channel B
01: Channel A
10: 2x Average output ((ChA + ChB) / 2)
11: 2x Average output ((ChA - ChB) / 2)
5-4DDC2 MUXR/W0These register bits set the input data source to the individual decimation filters.
00: Channel A
01: Channel B
10: 2x Average output ((ChA + ChB) / 2)
11: 2x Average output ((ChA - ChB) / 2)
3-2DDC1 MUXR/W0These register bits set the input data source to the individual decimation filters.
00: Channel B
01: Channel A
10: 2x Average output ((ChA + ChB) / 2)
11: 2x Average output ((ChA - ChB) / 2)
1-0DDC0 MUXR/W0These register bits set the input data source to the individual decimation filters.
00: Channel A
01: Channel B
10: 2x Average output ((ChA + ChB) / 2)
11: 2x Average output ((ChA - ChB) / 2)
Figure 7-96 Register 0x164
76543210
NCO3 UPDATENCO2 UPDATENCO1 UPDATENCO0 UPDATESEL NEG IM00NCO MODE
Table 7-47 Register 0x164 Field Descriptions
BitFieldTypeResetDescription
7NCO3 UPDATER/W0A '0' to '1' transition in these register bits updates the four NCO frequencies of the respective NCOs.
6NCO2 UPDATER/W0
5NCO1 UPDATER/W0
4NCO0 UPDATER/W0
3SEL NEG IMR/W0This field controls the selection of negative frequency image, and is applicable only in COMPLEX DDC model.
2-10R/W0Must write 0
0NCO MODER/W0This register configures the NCOs operating mode.
0: Phase continuous
1: Infinite phase coherent
Figure 7-97 Register 0x165
76543210
000LOW LATENCY EN0DIS NCO AUTO UPDATENCO SEL ENNCO COMMON UPDATE
Table 7-48 Register 0x165 Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
4LOW LATENCY ENR/W0This bit enables low latency mode by bypassing all digital features.
0: Normal operation
1: Enables low latency mode
30R/W0Must write 0
2DIS NCO AUTO UPDATER/W0This register bit disables the automatic update when switching the NCOs using GPIO pins
0: Normal operation
1: Automatic switch disabled
1NCO SEL ENR/W0This bit enables NCO frequency selection via SPI register 0x166 instead of GPIO pins.
0: NCO frequency selection via GPIO pins
1: NCO frequency selection via register 0x166.
0NCO COMMON UPDATER/W0A '0' to '1' transition in this register bit updates the four NCO frequencies of all NCOs.
Figure 7-98 Register 0x166
76543210
DDC3 NCO SELDDC2 NCO SELDDC1 NCO SELDDC0 NCO SEL
Table 7-49 Register 0x166 Field Descriptions
BitFieldTypeResetDescription
7-6DDC3 NCO SELR/W0These bits select which of the 4 frequencies are active in the respective DDCs/NCOs. The <NCO SEL EN> bit in register 0x165 (D1) has to be set also.
5-4DDC2 NCO SELR/W0
3-2DDC1 NCO SELR/W0
1-0DDC0 NCO SELR/W0
Figure 7-99 Register 0x167/168
76543210
DDC1/3 DECIMATIONDDC0/2 DECIMATION
Table 7-50 Register 0x167/0x168 Field Descriptions
BitFieldTypeResetDescription
7-4DDC1/3 DECIMATIONR/W0These bits set the decimation filter factors for the respective DDCs when using unequal decimation factors. Register <UNEQUAL DECIMATION> in register 0x169 (D7) has to be set also.
0000: DDC bypass
0001: Decimation by 2
0010: Decimation by 4
...
1110: Decimation by 16384
1111: Decimation by 32768
3-0DDC0/2 DECIMATIONR/W0
Figure 7-100 Register 0x169
76543210
UNEQUAL DECIMATION0NUM OF DDCSCOMMON DECIMATION
Table 7-51 Register 0x169 Field Descriptions
BitFieldTypeResetDescription
7UNEQUAL DECIMATIONR/W0This bit enables configuration of DDC0..3 to have unequal decimation factors.
0: Common decimation factor for all DDCs
1: Unequal decimation factors
60R/W0Must write 0
5-4NUM OF DDCSR/W00This register configures the # of active DDCs
00: Dual DDC Mode
01: Quad DDC Mode
10: Single DDC only (useful only when using internal 2x averaging)
11: not used
3-0COMMON DECIMATIONR/W0000This register bit set the decimation filter factors for all active DDCs.
0000: DDC bypass
0001: Decimation by 2
0010: Decimation by 4
...
1110: Decimation by 16384
1111: Decimation by 32768
Figure 7-101 Register 0x16B
76543210
000UPDATE NYQUIST ZONE0NYQUIST ZONE
Table 7-52 Register 0x16B Field Descriptions
BitFieldTypeResetDescription
7-50R/W0Must write 0
4UPDATE NYQUIST ZONER/W0This field must be pulsed after the Nyquist zone if programmed. A 0 to 1 transition on this bit copies the NYQUIST ZONE field to an internal register.
30R/W0Must write 0
2-0NYQUIST ZONER/W000This field controls the nyquist zone of operation. The internal calibration of the device depends on the NYQUIST ZONE of the signal being sampled. This field must be programmed based on the operating Nyquist zone
000: First Nyquist zone (from 0 to Fs/2)
001: Second Nyquist (from Fs/2 to Fs)
010: Third Nyquist (from Fs to 3Fs/2)
011:Fourth Nyquist (from 3Fs/2 to 2Fs)
100: Fifth Nyquist (from 2Fs to 5Fs/2)
101: Sixth Nyquist (from 5Fs/2 to 3Fs)
110,111: not used
Figure 7-102 Register 0x200..0x2DF
76543210
DDCx NCO FREQUENCYy [48:0]
DDCx NCO PHASEy [15:0]
Table 7-53 Register 0x200..0x2DF Field Descriptions
BitFieldTypeResetDescription
7-0DDCx NCO FREQUENCYy [48:0]R/W0These register bits configure the 48-bit frequency words for the four DDCs/NCOs. The format is little endian. The NCO frequency calculation is shown in Section 7.3.8.4.
7-0DDCx NCO PHASEy [15:0]R/W0These register bits configure the starting phase of the four frequency words for the four DDCs/NCOs. The format is little endian. The phase value is: 90° / <16-bit register>
Figure 7-103 Register 0x590
7 6 5 4 3 2 1 0
0 0 0 0 0 0 ENABLE DCLK DIVIDER 0
Table 7-54 Register 0x590 Field Descriptions
Bit Field Type Reset Description
7-2 0 R/W 0 Must write 0
1 ENABLE DCLK DIVIDER R/W 0 Setting this bit enables the DCLK divider. This is required for high decimation factors when the data bit clock (DCLK) of the LVDS interface is slower than the ADC sampling clock.
Figure 7-104 Register 0x691/0x692
7 6 5 4 3 2 1 0
LVDS PDN [5:7] DCLK PDN 0 0 0 0
0 0 0 LVDS PDN [0:4]
Table 7-55 Register 0x691/0x692 Field Descriptions
Bit Field Type Reset Description
7-0 LVDS PDN [0:7] R/W 0 These register bits power down the individual LVDS output lanes with LVDS pins in high impedance state as shown in Table 7-56. The remaining LVDS bus power down registers are in registers 0x113/0x114.
0: Normal operation
1: LVDS output lane powered down
4 DCLK PDN R/W 0 This bit powers down the LVDS output clock.
0: Normal operation
1: DCLK powered down
Table 7-56 LVDS power down register lane assignment
REG ADDR 0x113 0x114 0x691 0x692
REG BIT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
LVDS OUTPUT LANE 14 13 12 11 10 9 8 15 5 6 7 0 1 2 3 4