SBAS661C February 2015 – May 2021 ADS1262 , ADS1263
PRODUCTION DATA
The ADC1 offset calibration word is 24 bits, consisting of three 8-bit registers, as shown in Table 9-22. The offset value is twos complement format with a maximum positive value equal to 7FFFFFh (for negative offset), and a maximum negative value equal to 800000h (for positive offset). The 24-bit register is internally left-shifted to align with the 32-bit data before subtraction occurs. A register value equal to 000000h has no offset correction. Although the offset calibration register allows a wide range of offset values, the input signal cannot exceed ±106% of the precalibrated range in order to prevent ADC overrange. If chop mode is enabled, the offset calibration register is disabled. Table 9-23 shows example settings of the offset register.
REGISTER | BYTE ORDER | ADDRESS | BIT ORDER | |||||||
---|---|---|---|---|---|---|---|---|---|---|
OFCAL0 | LSB | 07h | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 (LSB) |
OFCAL1 | MID | 08h | B15 | B14 | B13 | B12 | B11 | B10 | B9 | B8 |
OFCAL2 | MSB | 09h | B23 (MSB) | B22 | B21 | B20 | B19 | B18 | B17 | B16 |
OFCAL[2:0] REGISTER VALUE | OFFSET CALIBRATED 32-BIT OUTPUT CODE(1) |
---|---|
000001h | FFFFFF00h |
000000h | 00000000h |
FFFFFFh | 00000100h |
The ADC2 offset calibration word is 16 bits, consisting of two 8-bit registers, as shown in Table 9-24. The 16-bit calibration value is internally aligned with the 24-bit ADC2 conversion result. The offset calibration value is subtracted from the conversion data.
REGISTER | BYTE ORDER | ADDRESS | BIT ORDER | |||||||
---|---|---|---|---|---|---|---|---|---|---|
ADC2OFC0 | LSB | 17h | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 (LSB) |
ADC2OFC1 | MSB | 18h | B15 | B14 | B13 | B12 | B11 | B10 | B9 | B8 |