SBAS706D April   2015  – April 2019 ADS54J60

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     FFT for 170-MHz Input Signal
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  AC Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Typical Characteristics
    10. 7.10 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
      5. 8.3.5 Power-Down Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
        1. 8.4.1.1 Serial Interface
        2. 8.4.1.2 Serial Register Write: Analog Bank
        3. 8.4.1.3 Serial Register Readout: Analog Bank
        4. 8.4.1.4 JESD Bank SPI Page Selection
        5. 8.4.1.5 Serial Register Write: JESD Bank
          1. 8.4.1.5.1 Individual Channel Programming
        6. 8.4.1.6 Serial Register Readout: JESD Bank
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Test Patterns
        3. 8.4.2.3 JESD204B Frame
        4. 8.4.2.4 JESD204B Frame
        5. 8.4.2.5 JESD204B Frame Assembly with Decimation
          1. 8.4.2.5.1 JESD Transmitter Interface
          2. 8.4.2.5.2 Eye Diagram
    5. 8.5 Register Maps
      1. 8.5.1 Example Register Writes
      2. 8.5.2 Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 0h (address = 0h)
            1. Table 20. Register 0h Field Descriptions
          2. 8.5.2.1.2 Register 1h (address = 1h)
            1. Table 21. Register 1h Field Descriptions
          3. 8.5.2.1.3 Register 2h (address = 2h)
            1. Table 22. Register 2h Field Descriptions
          4. 8.5.2.1.4 Register 3h (address = 3h)
            1. Table 23. Register 3h Field Descriptions
          5. 8.5.2.1.5 Register 4h (address = 4h)
            1. Table 24. Register 4h Field Descriptions
          6. 8.5.2.1.6 Register 5h (address = 5h)
            1. Table 25. Register 5h Field Descriptions
          7. 8.5.2.1.7 Register 11h (address = 11h)
            1. Table 26. Register 11h Field Descriptions
        2. 8.5.2.2 Master Page (080h) Registers
          1. 8.5.2.2.1  Register 20h (address = 20h), Master Page (080h)
            1. Table 27. Registers 20h Field Descriptions
          2. 8.5.2.2.2  Register 21h (address = 21h), Master Page (080h)
            1. Table 28. Register 21h Field Descriptions
          3. 8.5.2.2.3  Register 23h (address = 23h), Master Page (080h)
            1. Table 29. Register 23h Field Descriptions
          4. 8.5.2.2.4  Register 24h (address = 24h), Master Page (080h)
            1. Table 30. Register 24h Field Descriptions
          5. 8.5.2.2.5  Register 26h (address = 26h), Master Page (080h)
            1. Table 31. Register 26h Field Descriptions
          6. 8.5.2.2.6  Register 4Fh (address = 4Fh), Master Page (080h)
            1. Table 32. Register 4Fh Field Descriptions
          7. 8.5.2.2.7  Register 53h (address = 53h), Master Page (080h)
            1. Table 33. Register 53h Field Descriptions
          8. 8.5.2.2.8  Register 54h (address = 54h), Master Page (080h)
            1. Table 34. Register 54h Field Descriptions
          9. 8.5.2.2.9  Register 55h (address = 55h), Master Page (080h)
            1. Table 35. Register 55h Field Descriptions
          10. 8.5.2.2.10 Register 59h (address = 59h), Master Page (080h)
            1. Table 36. Register 59h Field Descriptions
        3. 8.5.2.3 ADC Page (0Fh) Register
          1. 8.5.2.3.1 Register 5F (address = 5F), ADC Page (0Fh)
            1. Table 37. Register 5F Field Descriptions
        4. 8.5.2.4 Main Digital Page (6800h) Registers
          1. 8.5.2.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
            1. Table 38. Register 0h Field Descriptions
          2. 8.5.2.4.2  Register 41h (address = 41h), Main Digital Page (6800h)
            1. Table 39. Register 41h Field Descriptions
          3. 8.5.2.4.3  Register 42h (address = 42h), Main Digital Page (6800h)
            1. Table 41. Register 42h Field Descriptions
          4. 8.5.2.4.4  Register 43h (address = 43h), Main Digital Page (6800h)
            1. Table 42. Register 43h Field Descriptions
          5. 8.5.2.4.5  Register 44h (address = 44h), Main Digital Page (6800h)
            1. Table 43. Register 44h Field Descriptions
          6. 8.5.2.4.6  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
            1. Table 44. Register 4Bh Field Descriptions
          7. 8.5.2.4.7  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
            1. Table 45. Register 4Dh Field Descriptions
          8. 8.5.2.4.8  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
            1. Table 46. Register 4Eh Field Descriptions
          9. 8.5.2.4.9  Register 52h (address = 52h), Main Digital Page (6800h)
            1. Table 47. Register 52h Field Descriptions
          10. 8.5.2.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
            1. Table 48. Register 72h Field Descriptions
          11. 8.5.2.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
            1. Table 49. Register ABh Field Descriptions
          12. 8.5.2.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
            1. Table 50. Register ADh Field Descriptions
          13. 8.5.2.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
            1. Table 51. Register F7h Field Descriptions
        5. 8.5.2.5 JESD Digital Page (6900h) Registers
          1. 8.5.2.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
            1. Table 52. Register 0h Field Descriptions
          2. 8.5.2.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
            1. Table 53. Register 1h Field Descriptions
          3. 8.5.2.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
            1. Table 55. Register 2h Field Descriptions
          4. 8.5.2.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
            1. Table 56. Register 3h Field Descriptions
          5. 8.5.2.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
            1. Table 57. Register 5h Field Descriptions
          6. 8.5.2.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
            1. Table 58. Register 6h Field Descriptions
          7. 8.5.2.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
            1. Table 59. Register 7h Field Descriptions
          8. 8.5.2.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
            1. Table 60. Register 16h Field Descriptions
          9. 8.5.2.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
            1. Table 61. Register 31h Field Descriptions
          10. 8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
            1. Table 62. Register 32h Field Descriptions
        6. 8.5.2.6 JESD Analog Page (6A00h) Registers
          1. 8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h)
            1. Table 63. Register 12h-15h Field Descriptions
          2. 8.5.2.6.2 Registers 13h-15h (address = 13h-15h), JESD Analog Page (6A00h)
            1. Table 64. Register 13h-15h Field Descriptions
          3. 8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h)
            1. Table 65. Register 16h Field Descriptions
          4. 8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h)
            1. Table 66. Register 17h Field Descriptions
          5. 8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
            1. Table 67. Register 1Ah Field Descriptions
          6. 8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
            1. Table 68. Register 1Bh Field Descriptions
        7. 8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers
          1. 8.5.2.7.1 Register 068h (address = 068h), Offset Read Page
            1. Table 69. Register 068h Field Descriptions
          2. 8.5.2.7.2 Register 069h (address = 069h), Offset Read Page
            1. Table 70. Register 069h Field Descriptions
          3. 8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page
            1. Table 71. Registers 074h, 076h, 078h, 7Ah Field Descriptions
          4. 8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page
            1. Table 72. Registers 075h, 077h, 079h, 7Bh Field Descriptions
        8. 8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers
          1. 8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page
            1. Table 73. Registers 00h, 04h, 08h, 0Ch Field Descriptions
          2. 8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page
            1. Table 74. Registers 01h, 05h, 09h, 0Dh Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
      4. 9.1.4 DC Offset Correction Block in the ADS54J60
        1. 9.1.4.1 Freezing the DC Offset Correction Block
        2. 9.1.4.2 Effect of Temperature
      5. 9.1.5 Idle Channel Histogram
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from C Revision (January 2017) to D Revision

  • Changed FFT for 170-MHz Input Signal figureGo
  • Changed the description of the CLKINM, CLKINP, SYSREFM, SYSREFP, and PDN pins in Pin Functions tableGo
  • Changed typical values across parameters in AC Characteristics tableGo
  • Changed value of AIN from –1 dBFS to –3 dBFS in 470 MHz test condition across all parameters in AC Characteristics tableGo
  • Added ENOB parameter to AC Characteristics table Go
  • Changed the first footnote in Timing Characteristics tableGo
  • Changed the typical value of FOVR latency from 18 + 4 ns to 18 in Timing Characteristics tableGo
  • Changed parameter name from tPD to tPDI in Timing Characteristics tableGo
  • Changed FFT for 170-MHz Input Signal figureGo
  • Changed FFT for 470-MHz Input Signal at –3 dBFS figure, title, and conditionsGo
  • Changed conditions of FFT for 720-MHz Input Signal at –6 dBFS figureGo
  • Changed Spurious-Free Dynamic Range vs Input Frequency figureGo
  • Changed DDC Block figureGo
  • Deleted register address 53 from Register Address for Power-Down Modes tableGo
  • Added last sentence to Step 4 in Serial Register Readout: Analog Bank sectionGo
  • Added last sentence to Step 4 in Serial Register Readout: JESD Bank section Go
  • Added SDOUT Timing Diagram figureGo
  • Deleted unrelated patterns in in JESD204B Test Patterns sectionGo
  • Changed Serial Interface Registers figureGo
  • Added register addresses 1h and 2h and their descriptions to GENERAL REGISTERS in Register Map sectionGo
  • Changed the name of MASTER PAGE (80h) to MASTER PAGE (ANALOG BANK PAGE SEL= 80h in Register Map tableGo
  • Changed register 53h and 54h, and their descriptions to MASTER PAGE (ANALOG BANK PAGE SEL = 80h) in Register Map sectionGo
  • Changed the name of ADC PAGE (0Fh) to ADC PAGE (ANALOG BANK PAGE SEL= 0Fh) in Register Map tableGo
  • Changed the name of MAIN DIGITAL PAGE (6800h) to MAIN DIGITAL PAGE (JESD BANK PAGE SEL=6800h) in Register Map tableGo
  • Changed bit 5, register 4E of MAIN DIGITAL PAGE (JESD BANK PAGE SEL = 6800h) from 0 to IMPROVE IL PERFGo
  • Changed the name of JESD DIGITAL PAGE (6900h) to JESD DIGITAL PAGE (JESD BANK PAGE SEL=6900h) in Register Map tableGo
  • Changed the name of JESD ANALOG PAGE (6A00h) to JESD ANALOG PAGE (JESD BANK PAGE SEL=6A00h) in Register Map tableGo
  • Changed bit 1, register 12 of JESD ANALOG PAGE (6A00h) from 0 to ALWAYS WRITE 1Go
  • Changed bits 5 and 3, register 17 of JESD ANALOG PAGE (JESD BANK PAGE SEL = 6A00h) from 0 to LANE PDN 1 and from 0 to LANE PDN 0 respectivelyGo
  • Added OFFSET READ Page and OFFSET LOAD Page registers to Register Map tableGo
  • Added ADS54J60 Access Type Codes table, deleted legends from Register Descriptions sectionGo
  • Added register 1h and 2h to Register Descriptions section Go
  • Changed description of Registers 3h and 4h (address = 3h and 4h) in General Registers PageGo
  • Changed description of bit 0 in Register 4Fh (address = 4Fh), Master Page (080h)Go
  • Changed the description of registers 53h and 54hGo
  • Changed 9.5 dB to 12 dB in description of bits 6-0 in Register 44h (address = 44h), Main Digital Page (6800h)Go
  • Changed bit 5 from 0 the IMPROVE IL PERF and changed Register 4Eh Field Descriptions table in Register 4Eh (address = 4Eh), Main Digital Page (6800h)Go
  • Changed bit 1 from 0 to ALWAYS WRITE 1 in Register 12h (address = 12h), JESD Analog Page (6A00h)Go
  • Changed bit 1 from ALWAYS WRITE 1 to 0 in register 15h bit register Go
  • Added x (where x = 0, 2, or 3) to bits 7-2 in Register 13h-15h Field Descriptions table of Registers 13h-15h (address = 13h-15h), JESD Analog Page (6A00h)Go
  • Changed bit 6 from W to R/W, bit 5 from 0 to LANE PDN 1 and from W to R/W, and changed bit 3 from 0 to LANE PDN 0 and from W to R/W in Register 17h bit register table of Register 17h (address = 17h), JESD Analog Page (6A00h)Go
  • Changed bits 5-0 of Register 17h Field Descriptions table in Register 17h (address = 17h), JESD Analog Page (6A00h)Go
  • Added Offset Read Page Register and Offset Load Page Register sections to Register Descriptions sectionGo
  • Added DC Offset Correction Block in the ADS54J60 sectionGo
  • Changed ±512 codes to ±1024 codes in DC Offset Correction Block in the ADS54J60 sectionGo
  • Added Idle Channel Histogram sectionGo
  • Added transformer TC1-1-13M+ to Transformer-Coupled Circuits sectionGo
  • Added note to Layout Guidelines sectionGo

Changes from B Revision (August 2015) to C Revision

  • Changed the SFDR value in the last sub-bullet of the Spectral Performance Features bulletGo
  • Changed Device Information tableGo
  • Added CDM row to ESD Ratings tableGo
  • Changed the minimum value for the input clock frequency in the Recommended Operating Conditions table Go
  • Added minimum value to the ADC sampling rate parameter in the Electrical Characteristics tableGo
  • Added 720 -MHz test condition rows to SNR, NSD, SINAD, SFDR, HD2, HD3, Non HD2, HD3, THD, and SFDR_IL parameters of AC Characteristics tableGo
  • Changed typical specification of SFDR parameter in AC Characteristics tableGo
  • Changed Sample Timing, Aperture jitter parameter typical specification in Timing Characteristics sectionGo
  • Added the FOVR latency parameter to the Timing Characteristics tableGo
  • Added FFT for 720-MHz Input Signal at –6 dBFS figureGo
  • Added Typical Characteristics: Contour sectionGo
  • Changed Overview section Go
  • Changed Functional Block Diagram section: changed Control and SPI block and added dashed outline to FOVR tracesGo
  • Added Figure 60 and text reference to Analog Inputs sectionGo
  • Changed SYSREF Signal section: changed Table 4 and added last paragraphGo
  • Added SYSREF Not Present (Subclass 0, 2) sectionGo
  • Changed the number of clock cycles in the Fast OVR sectionGo
  • Changed Table 10 and Table 11Go
  • Changed Table 12 and Table 13Go
  • Deleted Lane Enable with Decimation subsection Go
  • Added the Program Summary of DDC Modes and JESD Link Configuration tableGo
  • Added Figure 84 to Register Maps sectionGo
  • Changed Table 15Go
  • Deleted register 39h, 3Ah, and 56h Go
  • Changed Example Register Writes sectionGo
  • Updated register descriptions Go
  • Added Table 54Go
  • Deleted row for bit 1 in Table 64 as bit 1 is included in last table row Go
  • Changed Table 75Go
  • Changed internal aperture jitter value in SNR and Clock Jitter sectionGo
  • Changed Figure 141Go
  • Changed Power Supply Recommendations section Go
  • Added the Power Sequencing and Initialization sectionGo
  • Added Documentation Support and Receiving Notification of Documentation Updates sectionsGo

Changes from A Revision (May 2015) to B Revision

  • Released to production Go