SBAS707B June   2016  – January 2018 ADS8910B , ADS8912B , ADS8914B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Ease of System Design With ADS89xxB Integrated Features
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO Module
      2. 7.3.2 Reference Buffer Module
      3. 7.3.3 Converter Module
        1. 7.3.3.1 Sample-and-Hold Circuit
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 ADC Transfer Function
      4. 7.3.4 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Output Data Word
      2. 7.5.2 Data Transfer Frame
      3. 7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.4.2.3.2 Bus Width Options With SRC Protocols
            3. 7.5.4.2.3.3 Output Data Rate Options With SRC Protocols
      5. 7.5.5 Device Setup
        1. 7.5.5.1 Single Device: All multiSPI Options
        2. 7.5.5.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.5.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.5.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table 11. PD_CNTL Register Field Descriptions
        2. 7.6.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table 12. SDI_CNTL Register Field Descriptions
        3. 7.6.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table 13. SDO_CNTL Register Field Descriptions
        4. 7.6.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table 14. DATA_CNTL Register Field Descriptions
        5. 7.6.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table 15. PATN_LSB Register Field Descriptions
        6. 7.6.1.6 PATN_MID Register (address = 015h) [reset = 00h]
          1. Table 16. PATN_MID Register Field Descriptions
        7. 7.6.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table 17. PATN_MSB Register Field Descriptions
        8. 7.6.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table 18. OFST_CAL Register Field Descriptions
        9. 7.6.1.9 REF_MRG Register (address = 030h) [reset = 00h]
          1. Table 19. REF_MRG Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. 8.1.2.1 Charge-Kickback Filter
        2. 8.1.2.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.4.2.2 SPI-Compatible Protocols with Bus Width Options

The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual SDO) or four bits (quad SDO) when operating with any of the four legacy, SPI-compatible protocols.

Set the SDO_WIDTH[1:0] bits in the SDO_CNTL register to select the SDO bus width. The SCLK launch edge depends on the SPI protocol selection (as shown in Table 7).

Table 7. SPI-Compatible Protocols with Bus Width Options

PROTOCOLSCLK POLARITY
(At CS Falling Edge)		SCLK PHASE
(Capture Edge)		MSB BIT LAUNCH EDGESDI_CNTLSDO_CNTL#SCLK
(Optimal Read Frame)		TIMING DIAGRAM
SPI-00-D Low Rising CS falling 00h 08h 9 Figure 60
SPI-01-D Low Falling First SCLK rising 01h 08h 9 Figure 61
SPI-10-D High Falling CS falling 02h 08h 9 Figure 62
SPI-11-D High Rising First SCLK falling 03h 08h 9 Figure 63
SPI-00-Q Low Rising CS falling 00h 0Ch 5 Figure 64
SPI-01-Q Low Falling First SCLK rising 01h 0Ch 5 Figure 65
SPI-10-Q High Falling CS falling 02h 0Ch 5 Figure 66
SPI-11-Q High Rising First SCLK falling 03h 0Ch 5 Figure 67

In dual-SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and SDO-1) on every SCLK launch edge.

In quad-SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0, SDO-1, SDO-2, and SDO-3) on every SCLK launch edge.

ADS8910B ADS8912B ADS8914B SPI-00-2_bas707.gifFigure 60. SPI-00-D Protocol
ADS8910B ADS8912B ADS8914B SPI-10-2_bas707.gifFigure 62. SPI-10-D Protocol
ADS8910B ADS8912B ADS8914B SPI-00-4_bas707.gifFigure 64. SPI-00-Q Protocol
ADS8910B ADS8912B ADS8914B SPI-10-4_bas707.gifFigure 66. SPI-10-Q Protocol
ADS8910B ADS8912B ADS8914B SPI-01-2_bas707.gifFigure 61. SPI-01-D Protocol
ADS8910B ADS8912B ADS8914B SPI-11-2_bas707.gifFigure 63. SPI-11-D Protocol
ADS8910B ADS8912B ADS8914B SPI-01-4_bas707.gifFigure 65. SPI-01-Q Protocol
ADS8910B ADS8912B ADS8914B SPI-11-4_bas707.gifFigure 67. SPI-11-Q Protocol

For SDI_MODE[1:0] = 00b or 10b, the device supports an early data launch (EDL) option. Set SDO_MODE[1:0] = 01b in the SDO_CNTL register to enable the feature (see Table 8). Setting SDO_MODE[1:0] = 01b has no effect if SDI_MODE[1:0] = 01b or 11b.

Table 8. SPI Protocols with Early Data Launch

PROTOCOLSCLK POLARITY
(At CS Falling Edge)		SCLK PHASE
(Capture Edge)		MSB BIT LAUNCH EDGESDI_CNTLSDO_CNTLNO. OF SCLK
(Optimal Read Frame)		TIMING DIAGRAM
SPI-00-D-EDL Low Rising CS falling 00h 09h 9 Figure 60
SPI-10-D-EDL High Falling CS falling 02h 09h 9 Figure 62
SPI-00-Q-EDL Low Rising CS falling 00h 0Dh 5 Figure 64
SPI-10-Q-EDL High Falling CS falling 02h 0Dh 5 Figure 66

As shown in Figure 58, and Figure 59, the device launches the output data bits on the SDO-x pins half clock earlier compared to the standard SPI protocol.

ADS8910B ADS8912B ADS8914B SPI-00-2-EDL_bas707.gifFigure 68. SPI-00-D-EDL Protocol
ADS8910B ADS8912B ADS8914B SPI-00-4-EDL_bas707.gifFigure 70. SPI-00-Q-EDL Protocol
ADS8910B ADS8912B ADS8914B SPI-10-2-EDL_bas707.gifFigure 69. SPI-10-D-EDL Protocol
ADS8910B ADS8912B ADS8914B SPI-10-4-EDL_bas707.gifFigure 71. SPI-10-Q-EDL Protocol

When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer frame; see the Timing Requirements and Switching Characteristics tables for associated timing parameters.

Figure 60 to Figure 71 illustrate how the wider data bus allows the host controller to read all 22 bits of the output data word using shorter data transfer frames. Table 7 and Table 8 show the number of SCLK required in an optimal read frame for the different output protocol selections.

NOTE

With SDO_CNTL[7:0] ≠ 00h or 01h, a long data transfer frame does not result in daisy-chain operation. On SDO pin (or pins), the 22 bits of output data word are followed by zeros.