SLASFA1 july   2023 AFE539F1-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADC Input
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Analog-to-Digital Converter (ADC) Mode
        1. 7.4.1.1 Voltage Reference Selection
          1. 7.4.1.1.1 Power-Supply as Reference
          2. 7.4.1.1.2 Internal Reference
          3. 7.4.1.1.3 External Reference
      2. 7.4.2 Pulse-Width Modulation (PWM) Mode
      3. 7.4.3 Constant Power-Dissipation Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  REF-GAIN-CONFIG Register (address = 15h) [reset = 0401h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 13FFh]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      11. 7.6.11 MAX-OUTPUT Register (SRAM address = 20h) [reset = 007Fh]
      12. 7.6.12 MIN-OUTPUT Register (SRAM address = 21h) [reset = 0000h]
      13. 7.6.13 FUNCTION-COEFFICIENT Register (SRAM address = 22h) [reset = 01F4h]
      14. 7.6.14 PWM-FREQUENCY Register (SRAM address = 23h) [reset = 000Bh]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

Use VDD (5 V) as reference with gain 1 × to achieve an input range of (VDD/3) = 1.67 V, using Table 7-1. With a bus voltage of 48 V and ADC input range of 1.67 V, the external attenuation required is 28.74. Therefore, the attenuation resistors can be chosen as RA = 100 kΩ and RB = 3.6 kΩ. To limit the power dissipation to 50 W, the effective load resistance (RL-eff) is calculated as (VBUS2/P) = 46.08 Ω. That means a minimum duty-cycle of (RL/RL-eff ) = 10.85% is required. In a 7-bit scale, 10.85% corresponds to 13.89d. The required function coefficient, K can be calculated using Equation 4 to be 443.6d (0x01BC).

Equation 4. K = D M I N × A D C - D A T A M A X 2 2 15

The PWM output pin is an open drain output. The PWM output pin must be pulled up to the desired IO voltage using an external resistor. The PWM frequency is set in the PWM-FREQUENCY SRAM location (SRAM: 0x23). Table 7-2 defines the codes for each available frequency. This example uses a PWM frequency of 3.052 kHz. Set the maximum and minimum PWM duty cycles limits in the MAX-OUTPUT and MIN-OUTPUT SRAM locations. The PWM duty cycle output is configured by a 7-bit code. The maximum code is 127d. 127d sets the PWM duty cycle to 100%. Table 7-3 provides more details about PWM duty cycle computation in AFE539F1-Q1.

Follow these guidelines to setup the registers on AFE539F1-Q1:

  • Set the VREF/MODE pin low to enable the digital pins for programming mode.
  • Stop the state machine before updating the application parameters by writing 0 to the STATE-MACHINE-CONFIG0 register.
  • If the PWM generator is already running, stop the PWM generator before any changes to the PWM frequency take effect. Write a 0 to the START-FUNCTION field in the COMMON-PWM-TRIG register (0x21) to stop the PWM generator. The PWM generator automatically starts when the state machine is enabled.
  • Set all of the application parameters shown in Table 8-2. Use these locations to save the settings in NVM.
  • Configure the reference for the ADC in the REF-GAIN-CONFIG register.
  • Power on the ADC channel using the COMMON-CONFIG register.
  • Start the state machine by writing 0x3 to the STATE-MACHINE-CONFIG0.
  • Trigger an NVM write by setting the NVM-PROG bit in the COMMON-TRIGGER register (0x20) to 1.
  • Set the VREF/MODE pin high to enable the digital pins for standalone mode. This is required to see the PWM output on the digital pin.

Table 8-2 Application Parameters
REGISTER FIELD NAME ADDRESS[FIELD] ADDRESS LOCATION
MAX-OUTPUT 0x20[6:0] SRAM
MIN-OUTPUT 0x21[6:0] SRAM
FUNCTION-COEFFICIENT 0x22[15:0] SRAM
PWM-FREQUENCY 0x23[4:0] SRAM
REF-GAIN-CONFIG 0x15[12:10][4:0] Register
COMMON-CONFIG 0x1F[15:0] Register
STATE-MACHINE-CONFIG0 0x27[2:0] Register

The pseudocode for this application example is as follows: 

//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <MSB DATA>, <LSB DATA>
//Stop the state machine
WRITE STATE-MACHINE-CONFIG0(0x27), 0x00, 0x01
//Stop the PWM generator
WRITE COMMON-PWM-TRIG(0x21), 0x00, 0x00
//Set the PWM frequncy to 3.052 kHz 
WRITE PWM-FREQUENCY(SRAM 0x23), 0x00, 0x07
//Set the maximim and minimum PWM duty cycles
WRITE MAX-OUTPUT(SRAM 0x20), 0x00, 0x7F
WRITE MIN-OUTPUT(SRAM 0x21), 0x00, 0x00
//Set the function coefficient (K)
WRITE FUNCTION-COEFFICIENT(SRAM 0x22), 0x01, 0xBC
//Set the ADC reference to VDD (this is the device default) 
WRITE REF-GAIN-CONFIG(0x15), 0x04, 0x01
//Power on ADC 
WRITE COMMON-CONFIG(0x1F), 0x03, 0xFF
//Start the state machine
WRITE STATE-MACHINE-CONFIG0(0x27), 0x00, 0x03
//Save settings to NVM
WRITE COMMON-TRIGGER(0x20), 0x00, 0x02
//Pull the VREF/MODE pin high to enter standalone mode