SBASAW1A September   2023  – December 2023 AMC21C12

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information 
    5. 5.5 Package Characteristics
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics 
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Reference Input
      3. 6.3.3 Isolation Channel Signal Transmission
      4. 6.3.4 Open-Drain Digital Output
        1. 6.3.4.1 Transparent Output Mode
        2. 6.3.4.2 Latch Output Mode
      5. 6.3.5 Power-Up and Power-Down Behavior
      6. 6.3.6 VDD1 Brownout and Power-Loss Behavior
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Overcurrent Detection
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Overvoltage Detection
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DEN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 Reference Input

The voltage on the REF pin determines the trip threshold of the window comparator. The internal precision current source forces a 100-μA current through an external resistor connected from the REF pin to GND1. The resulting voltage across the resistor (VREF) equals the magnitude of the positive and negative trip thresholds, see Figure 6-1. Place a 100-nF capacitor parallel to the resistor to filter the reference voltage. This capacitor must be charged by the 100-μA current source during power-up and the charging time may exceed the high-side blanking time (tHS,BLK). In this case, as shown in Figure 6-2, the comparator may output an incorrect state after the high-side blanking time has expired until VREF reaches the final value. See the Open-Drain Digital Output Open-Drain Digital Output Transparent Output ModeLatch Output ModePower-Up and Power-Down BehaviorVDD1 Brownout and Power-Loss Behavior Open-Drain Digital Output section for more details on power-up behavior.

GUID-20211105-SS0I-LJWF-QSN6-L1LR3XMFFQGJ-low.svg Figure 6-2 Output Behavior for Long Settling Times of the Reference Voltage

The voltage on the REF pin also determines the functionality of the negative comparator (Cmp1) and the hysteresis of the positive comparator (Cmp0) shown in the Functional Block Diagram. If VREF exceeds the VMSEL threshold defined in the Electrical Characteristics table, Cmp1 is disabled and the hysteresis of Cmp0 is increased from 4 mV (typical) to 25 mV. Positive-comparator mode is intended for voltage-monitoring applications that require higher input voltages and higher noise immunity.

The reference pin can be driven by an external voltage source to change the comparator thresholds during operation. However, do not drive VREF dynamically across the VMSEL threshold during normal operation because doing so changes the hysteresis of the Cmp0 comparator and can lead to unintentional switching of the output.

Figure 6-3 shows a mode selection timing diagram.

GUID-20210504-CA0I-G03R-8TRL-RPQWTNLNH41H-low.svg Figure 6-3 Mode Selection