SBASAX2A November 2023 – March 2024 DAC39RF10EF , DAC39RFS10EF
PRODUCTION DATA
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction specifies the access type, register address, and data value as normal. Additional clock cycles of write or read data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming transaction. The ASCEND bit (register 000h, bit 5) controls whether the address value ascends (increments) or descends (decrements). Figure 7-59 shows the streaming mode transaction details.