SLASF60 april   2023 DAC53204-Q1 , DAC63204-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Digital Input/Output
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 Comparator Mode
        1. 7.4.3.1 Programmable Hysteresis Comparator
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 Fault-Dump Mode
      5. 7.4.5 Application-Specific Modes
        1. 7.4.5.1 Voltage Margining and Scaling
          1. 7.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 Function Generation
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 Device Reset and Fault Management
        1. 7.4.6.1 Power-On Reset (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 7.4.7 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
      3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
      20. 7.6.20 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      21. 7.6.21 PMBUS-PAGE Register [reset = 0300h]
      22. 7.6.22 PMBUS-OP-CMD-X Register [reset = 0000h]
      23. 7.6.23 PMBUS-CML Register [reset = 0000h]
      24. 7.6.24 PMBUS-VERSION Register [reset = 2200h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.4.5.1.3 PMBus Compatibility Mode

The PMBus protocol is an I2C-based communication standard for power-supply management. PMBus contains standard command codes tailored to power supply applications. The DACx3204‑Q1 implement some PMBus commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as well as PMBUS revision. Figure 7-11 shows typical PMBus connections. The EN-PMBUS bit in the INTERFACE-CONFIG register must be set to 1 to enable the PMBus protocol.

GUID-20211130-SS0I-M7LR-MHV2-VJJ7SLSM6RT1-low.svg Figure 7-11 PMBus Connections

Similar to I2C, PMBus is a variable length packet of 8-bit data bytes, each with a receiver acknowledge, wrapped between a start and stop bit. The first byte is always a 7-bit target address followed by a write bit, sometimes called the even address that identifies the intended receiver of the packet. The second byte is an 8-bit command byte, identifying the PMBus command being transmitted using the respective command code. After the command byte, the transmitter either sends data associated with the command to write to the receiver command register (from least significant byte to most significant byte, as shown in Table 7-14), or sends a new start bit indicating the desire to read the data associated with the command register from the receiver. Then the receiver transmits the data following the same least significant byte first format (see Table 7-17).

Table 7-7 PMBus Update Sequence
MSB ... LSB ACK MSB ... LSB ACK MSB ... LSB ACK MSB ... LSB ACK
Address (A) byte
Section 7.5.2.2.1		 Command byte
Section 7.5.2.2.2		 Data byte - LSDB Data byte - MSDB (Optional)
DB [31:24] DB [23:16] DB [15:8] DB [7:0]
Table 7-8 PMBus Read Sequence
S MSB … R/W (0) ACK MSB … LSB ACK Sr MSB … R/W (1) ACK MSB … LSB ACK MSB … LSB ACK
ADDRESS BYTE
Section 7.5.2.2.1		 COMMAND BYTE
Section 7.5.2.2.2		 Sr ADDRESS BYTE
Section 7.5.2.2.1		 LSDB MSDB (Optional)
From Controller Target From Controller Target From Controller Target From Target Controller From Target Controller

The DACx3204‑Q1 I2C interface implements some of the PMBus commands. Table 7-9 shows the supported PMBus commands that are implemented in DACx3204‑Q1. The DAC uses DAC-X-MARGIN-LOW, DAC-X-MARGIN-HIGH bits, SLEW-RATE-X, and CODE-STEP-X bits for PMBUS-OPERATION-CMD-X. To access multiple channels, write the PMBus page address as specified in the Register Names table in the Register Map section to the PMBUS-PAGE register first, followed by a write to the channel-specific register.

Table 7-9 PMBus Operation Commands
REGISTER PMBUS-OPERATION-CMD-X[15:8] DESCRIPTION
PMBUS-OP-CMD-X 00h Turn off
80h Turn on
94h Margin low
A4h Margin high

The DACx3204‑Q1 also implement PMBus features such as group command protocol and communication time-out failure. The CML bit in the PMBUS-CML register indicates a communication fault in the PMBus. This bit is reset by writing 1.

To get the PMBus version, read the PMBUS-VERSION register.