SBAS438C May   2008  – November 2019 DAC9881

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: AVDD = 5 V
    6. 6.6  Electrical Characteristics: AVDD = 2.7 V
    7. 6.7  Timing Requirements—Standalone Operation Without SDO
    8. 6.8  Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode
    9. 6.9  Typical Characteristics: AVDD = 5 V
    10. 6.10 Typical Characteristics: AVDD = 2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
        1. 7.3.6.1 Program Reset Value
      7. 7.3.7  Power Down
      8. 7.3.8  Double-Buffered Interface
        1. 7.3.8.1 Load DAC Pin (LDAC)
          1. 7.3.8.1.1 Synchronous Mode
          2. 7.3.8.1.2 Asynchronous Mode
      9. 7.3.9  1.8-V to 5-V Logic Interface
      10. 7.3.10 Power-Supply Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using the DAC9881
    2. 8.2 Typical Application
      1. 8.2.1 DAC9881 Sample-and-Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Reference Inputs

The reference high input, VREFH, can be set to any voltage in the range of 1.25 V to AVDD. The reference low input, VREFL, can be set to any voltage in the range of –0.2 V to +0.2 V (to provide a small offset to the output of the DAC9881, if desired). The current into VREFH and out of VREFL depends on the DAC code, and can vary from approximately 0.5 mA to 1 mA in the gain = 1X mode of operation. The reference high and low inputs appear as variable loads to the external reference circuit. If the external references can source or sink the required current, and if low impedance connections are made to the VREFH and VREFL pins, external reference buffers are not required. Figure 65 shows a simple configuration of the DAC9881 using external references without force and sense reference buffers.

Kelvin sense connections for the reference high and low are included on the DAC9881. When properly used with external reference buffer op amps, these reference Kelvin sense pins make sure that the driven reference high and low voltages remain stable versus varying reference load currents. Figure 67 shows an example of a reference force and sense configuration of the DAC9881 operating from a single analog reference voltage. Both the VREFL and VREFH reference voltages are set to levels of 100 mV from the DAC9881 supply rails, and are derived from a 5-V external reference. Figure 68 illustrates the effect of not using the reference force and sense buffers to drive the DAC9881 VREFL and VREFH pins. Figure 69 shows the improvement when using the reference buffers. A slight degradation in INL and DNL performance is seen without the use of the force and sense buffer configuration.

DAC9881 ai_buf_ref_bas438.gifFigure 67. Buffered References (VREFH = +4.900 V and VREFL = 100 mV).
DAC9881 ai_inl_dnl_1_bas438.gifFigure 68. Linearity and Differential Linearity Error
for Figure 65 Without Reference Buffers
DAC9881 ai_inl_dnl_2_bas438.gifFigure 69. Linearity and Differential Linearity Error
for Figure 67 With Reference Buffers