DLPS153 October   2023 DLP651LE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Optical Interface and System Image Quality Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 Micromirror Array Temperature Calculation
    6. 7.6 Micromirror Power Density Calculation
    7. 7.7 Window Aperture Illumination Overfill Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
  11. 10Power Supply Recommendations
    1. 10.1 DMD Power Supply Power-Up Procedure
    2. 10.2 DMD Power Supply Power-Down Procedure
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • FYM|149
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1)
MIN MAX UNIT
SUPPLY VOLTAGES
VCC Supply voltage for LVCMOS core logic(2) –0.5 4 V
VCCI Supply voltage for LVDS interface(2) –0.5 4 V
VOFFSET Micromirror electrode and HVCMOS voltage(2)(3) –0.5 9 V
VMBRST Input voltage for MBRST(15:0)(2) –28 28 V
|VCCI – VCC| Supply voltage delta (absolute value)(4) 0.3 V
INPUT VOLTAGES
Input voltage for all other input pins(2) –0.5 VCC + 0.3 V
|VID| Input differential voltage (absolute value)(5) 700 mV
CLOCKS
ƒCLOCK Clock frequency for LVDS interface, DCLK_A 400 MHz
ƒCLOCK Clock frequency for LVDS interface, DCLK_B 400 MHz
ENVIRONMENTAL
TARRAY Temperature, operating(6) 0 90 °C
Temperature, non-operating(6) –40 90 °C
TDP Dew point temperature, operating and non-operating (noncondensing) 81 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for all DMD operating modes.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable voltage difference between VCC and VCCI may result in excessive current draw.
(5) The maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
(6) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1), shown in the figure in Section 7.5.