DLPS241 april   2023 DLP670RE

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Requirements
    1. 9.1 DMD Power Supply Requirements
    2. 9.2 DMD Power Supply Power-Up Procedure
    3. 9.3 DMD Power Supply Power-Down Procedure
  10. 10Device Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FYE|350
Thermal pad, mechanical data (Package|Pins)

5 Pin Configuration and Functions

GUID-D5487C86-6F22-4575-A229-8025F5F0BE42-low.gifFigure 5-1 FYE Package350-PinBottom View
Table 5-1 Pin Functions
PIN(1)TYPE(5)SIGNALDATA RATE(2)INTERNAL TERM(3)DESCRIPTIONTRACE (mils)(4)
NAMENO.
DATA BUS A
D_AN(0)B14ILVDSDDRDifferentialData, negative494.88
D_AN(1)B15IDDRDifferentialData, negative486.18
D_AN(2)C16IDDRDifferentialData, negative495.16
D_AN(3)K24IDDRDifferentialData, negative485.67
D_AN(4)B18IDDRDifferentialData, negative494.76
D_AN(5)L24IDDRDifferentialData, negative490.63
D_AN(6)C19IDDRDifferentialData, negative495.16
D_AN(7)H24IDDRDifferentialData, negative485.55
D_AN(8)H23IDDRDifferentialData, negative495.16
D_AN(9)B25IDDRDifferentialData, negative485.59
D_AN(10)D24IDDRDifferentialData, negative495.16
D_AN(11)E25IDDRDifferentialData, negative495.16
D_AN(12)F25IDDRDifferentialData, negative490.04
D_AN(13)H25IDDRDifferentialData, negative485.91
D_AN(14)L25IDDRDifferentialData, negative495.16
D_AN(15)G24IDDRDifferentialData, negative495.16
D_AP(0)C14ILVDSDDRDifferentialData, positive494.84
D_AP(1)B16IDDRDifferentialData, positive486.22
D_AP(2)C17IDDRDifferentialData, positive494.65
D_AP(3)K23IDDRDifferentialData, positive488.42
D_AP(4)B19IDDRDifferentialData, positive495.16
D_AP(5)L23IDDRDifferentialData, positive490.67
D_AP(6)C20IDDRDifferentialData, positive498.11
D_AP(7)J24IDDRDifferentialData, positive486.22
D_AP(8)J23IDDRDifferentialData, positive495.47
D_AP(9)C25IDDRDifferentialData, positive485.94
D_AP(10)E24IDDRDifferentialData, positive495.16
D_AP(11)D25IDDRDifferentialData, positive494.13
D_AP(12)G25IDDRDifferentialData, positive488.98
D_AP(13)J25IDDRDifferentialData, positive492.56
D_AP(14)K25IDDRDifferentialData, positive495.16
D_AP(15)F24IDDRDifferentialData, positive495.16
DATA BUS B
D_BN(0)Z14ILVDSDDRDifferentialData, negative494.92
D_BN(1)Z15IDDRDifferentialData, negative486.18
D_BN(2)Y16IDDRDifferentialData, negative496.46
D_BN(3)P24IDDRDifferentialData, negative493.74
D_BN(4)Z18IDDRDifferentialData, negative494.76
D_BN(5)N24IDDRDifferentialData, negative495.16
D_BN(6)Y19IDDRDifferentialData, negative492.16
D_BN(7)T24IDDRDifferentialData, negative492.68
D_BN(8)T23IDDRDifferentialData, negative484.45
D_BN(9)Z25IDDRDifferentialData, negative492.09
D_BN(10)X24IDDRDifferentialData, negative497.72
D_BN(11)W25IDDRDifferentialData, negative495.16
D_BN(12)V25IDDRDifferentialData, negative484.17
D_BN(13)T25IDDRDifferentialData, negative481.42
D_BN(14)N25IDDRDifferentialData, negative495.16
D_BN(15)U24IDDRDifferentialData, negative489.8
D_BP(0)Y14ILVDSDDRDifferentialData, positive494.88
D_BP(1)Z16IDDRDifferentialData, positive486.26
D_BP(2)Y17IDDRDifferentialData, positive495.16
D_BP(3)P23IDDRDifferentialData, positive492.48
D_BP(4)Z19IDDRDifferentialData, positive495.16
D_BP(5)N23IDDRDifferentialData, positive497.99
D_BP(6)Y20IDDRDifferentialData, positive495.16
D_BP(7)R24IDDRDifferentialData, positive492.05
D_BP(8)R23IDDRDifferentialData, positive484.45
D_BP(9)Y25IDDRDifferentialData, positive492.24
D_BP(10)W24IDDRDifferentialData, positive495.16
D_BP(11)X25IDDRDifferentialData, positive494.72
D_BP(12)U25IDDRDifferentialData, positive483.78
D_BP(13)R25IDDRDifferentialData, positive489.13
D_BP(14)P25IDDRDifferentialData, positive499.53
D_BP(15)V24IDDRDifferentialData, positive488.66
SERIAL CONTROL
SCTRL_ANC23ILVDSDDRDifferentialSerial control, negative492.95
SCTRL_BNY23IDDRDifferentialSerial control, negative493.78
SCTRL_APC24IDDRDifferentialSerial control, negative493.78
SCTRL_BPY24IDDRDifferentialSerial control, negative493.11
CLOCKS
DCLK_ANB23ILVDSDifferentialClock, negative480.35
DCLK_BNZ23IDifferentialClock, negative486.22
DCLK_APB22IDifferentialClock, negative485.83
DCLK_BPZ22IDifferentialClock, negative491.93
SERIAL COMMUNICATIONS PORT (SCP)
SCP_DOB8OLVCMOSSDRSerial communications port output
SCP_DIB7ISDRPulldownSerial communication port data I
SCP_CLKB6ISerial communications port clock
SCP_ENZC8IActive-low serial communications port enable
MICROMIRROR RESET CONTROL
RESET_ADDR(0)X9ILVCMOSPulldownReset driver address select
RESET_ADDR(1)X8IReset driver address select
RESET_ADDR(2)Z8IReset driver address select
RESET_ADDR(3)Z7IReset driver address select
RESET_MODE(0)W11IReset driver mode select
RESET_MODE(1)Z10IReset driver mode select
RESET_SEL(0)Y10IReset driver level select
RESET_SEL(1)Y9IReset driver level select
RESET_STROBEY7IReset address, mode, and level latched on rising-edge
ENABLES AND INTERRUPTS
PWRDNZD2ILVCMOSPulldownActive-low device reset
RESET_OEZW7IPulldownActive-low output enable for DMD reset driver circuits
RESETZZ6IPulldownActive-low sets reset circuits in known VOFFSET state
RESET_IRQZZ5OActive-low, output interrupt to ASIC
VOLTAGE REGULATOR MONITORING
PG_BIASE11ILVCMOSPullupActive-low fault from external VBIAS regulator
PG_OFFSETB10IActive-low fault from external VOFFSET regulator
PG_RESETD11IActive low from external VRESET regulator
EN_BIASD9OActive-high enable for external VBIAS regulator
EN_OFFSETC9OActive-high enable for external VOFFSET regulator
EN_RESETE9OActive-high enable for external VRESET regulator
LEAVE PIN UNCONNECTED
MBRST(0)C2OAnalogPulldownFor proper DMD operation, do not connect.
MBRST(1)C3O
MBRST(2)C5O
MBRST(3)C4O
MBRST(4)E5O
MBRST(5)E4O
MBRST(6)E3O
MBRST(7)G4O
MBRST(8)G3O
MBRST(9)G2O
MBRST(10)J4O
MBRST(11)J3O
MBRST(12)J2O
MBRST(13)L4O
MBRST(14)L3O
MBRST(15)L2O
LEAVE PIN UNCONNECTED
RESERVED_PFEE7ILVCMOSPulldownFor proper DMD operation, do not connect.
RESERVED_TMD13I
RESERVED_Xl1E13I
RESERVED_TP0W12IAnalog
RESERVED_TP1Y11I
RESERVED_TP2X11I
LEAVE PIN UNCONNECTED
RESERVED_BAY12OLVCMOSFor proper DMD operation, do not connect.
RESERVED_BBC12O
RESERVED_TSD5O
LEAVE PIN UNCONNECTED
NO CONNECTB11For proper DMD operation, do not connect.
NO CONNECTC11
NO CONNECTC13
NO CONNECTE12
NO CONNECTE14
NO CONNECTE23
NO CONNECTH4For proper DMD operation, do not connect.
NO CONNECTN2
NO CONNECTN3
NO CONNECTN4
NO CONNECTR2
NO CONNECTR3
NO CONNECTR4
NO CONNECTT4
NO CONNECTU2For proper DMD operation, do not connect.
NO CONNECTU3
NO CONNECTU4
NO CONNECTW3
NO CONNECTW4
NO CONNECTW5
NO CONNECTW13
NO CONNECTW14
NO CONNECTW23
NO CONNECTX4For proper DMD operation, do not connect.
NO CONNECTX5
NO CONNECTX13
NO CONNECTY2
NO CONNECTY3
NO CONNECTY4
NO CONNECTY5
NO CONNECTZ11
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected.
(2) DDR = Double Data Rate. SDR = Single Data Rate. Refer to Section 6.7 for specifications and relationships.
(3) Internal term—CMOS level internal termination. Refer to Section 6.4 for differential termination specification.
(4) Dielectric Constant for the DMD FYE package is approximately 9.6. For the package trace lengths shown: Propagation Speed = 11.8 / sqrt(9.6) = 3.808 in/ns. Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.
(5) I = Input, O = Output, G = Ground
Table 5-2 Power Pin Functions
PINTYPE (I/O/P)(2)SIGNALDESCRIPTION
NAME(1)NO.
VBIASA6, A7, A8, AA6, AA7, AA8PAnalogSupply voltage for positive Bias level of micromirror reset signal
VOFFSETA3, A4, A25AnalogSupply voltage for HVCMOS logic
B26, L26, M26AnalogSupply voltage for stepped high voltage at micromirror address electrodes
N26, Z26, AA3, AA4AnalogSupply voltage for positive Offset level of micromirror reset signal
VRESETG1, H1, J1, R1, T1, U1AnalogSupply voltage for negative Reset level of micromirror reset signal
VCCA9, B3, B5, B12, C1, C6, C10, D4, D6, D8, E1, E2, E10, E15, E16, E17, F3, H2, K1, K3, M4, P1, P3, T2, V3, W1, W2, W6, W9, W10, W15, W16, W17, X3, X6, Y1, Y8, Y13, Z1, Z3, Z12, AA2, AA9, AA10AnalogSupply voltage for LVCMOS core logic. Supply voltage for normal high level at micromirror address electrodes. Supply voltage for positive Offset level of micromirror reset signal during power-down sequence
VCCIA16, A17, A18, A20, A21, A23, AA16, AA17, AA18, AA20, AA21, AA23AnalogSupply voltage for LVDS receivers
VSSA5, A10, A11, A19, A22, A24, B2, B4, B9, B13, B17, B20, B21, B24, C7, C15, C18, C21, C22, C26, D1, D3, D7, D10, D12, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D26, E6, E8, E18, E19, E20, E21, E22, E26, F1, F2, F4, F23, F26, G23, G26, H3, H26, J26, K2, K4, K26, L1, M1, M2, M3, M23, M24, M25, N1, P2, P4, P26, R26, T3, T26, U23, U26, V1, V2, V4, V23, V26, W8, W18, W19, W20, W21, W22, W26, X1, X2, X7, X10, X12, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X26, Y6, Y15, Y18, Y21, Y22, Y26, Z2, Z4, Z9, Z13, Z17, Z20, Z21, Z24, AA5, AA11, AA19, AA22, AA24AnalogDevice ground. Common return for all power
(1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected.
(2) P = Power