SNLS647G december   2019  – july 2023 DP83826E , DP83826I

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Mode Comparison Tables
  7. 6 Pin Configuration and Functions (ENHANCED Mode)
  8. 7 Pin Configuration and Functions (BASIC Mode)
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 9.3.2  Auto-MDIX Resolution
      3. 9.3.3  Energy Efficient Ethernet
        1. 9.3.3.1 EEE Overview
        2. 9.3.3.2 EEE Negotiation
      4. 9.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 9.3.5  Wake-on-LAN Packet Detection
        1. 9.3.5.1 Magic Packet Structure
        2. 9.3.5.2 Magic Packet Example
        3. 9.3.5.3 Wake-on-LAN Configuration and Status
      6. 9.3.6  Low Power Modes
        1. 9.3.6.1 Active Sleep
        2. 9.3.6.2 IEEE Power-Down
        3. 9.3.6.3 Deep Power Down State
      7. 9.3.7  RMII Repeater Mode
      8. 9.3.8  Clock Output
      9. 9.3.9  Media Independent Interface (MII)
      10. 9.3.10 Reduced Media Independent Interface (RMII)
      11. 9.3.11 Serial Management Interface
        1. 9.3.11.1 Extended Register Space Access
        2. 9.3.11.2 Write Address Operation
        3. 9.3.11.3 Read Address Operation
        4. 9.3.11.4 Write (No Post Increment) Operation
        5. 9.3.11.5 Read (No Post Increment) Operation
        6. 9.3.11.6 Example Write Operation (No Post Increment)
      12. 9.3.12 100BASE-TX
        1. 9.3.12.1 100BASE-TX Transmitter
          1. 9.3.12.1.1 Code-Group Encoding and Injection
          2. 9.3.12.1.2 Scrambler
          3. 9.3.12.1.3 NRZ to NRZI Encoder
          4. 9.3.12.1.4 Binary to MLT-3 Converter
        2. 9.3.12.2 100BASE-TX Receiver
      13. 9.3.13 10BASE-Te
        1. 9.3.13.1 Squelch
        2. 9.3.13.2 Normal Link Pulse Detection and Generation
        3. 9.3.13.3 Jabber
        4. 9.3.13.4 Active Link Polarity Detection and Correction
      14. 9.3.14 Loopback Modes
        1. 9.3.14.1 Near-end Loopback
        2. 9.3.14.2 MII Loopback
        3. 9.3.14.3 PCS Loopback
        4. 9.3.14.4 Digital Loopback
        5. 9.3.14.5 Analog Loopback
        6. 9.3.14.6 Far-End (Reverse) Loopback
      15. 9.3.15 BIST Configurations
      16. 9.3.16 Cable Diagnostics
        1. 9.3.16.1 Time Domain Reflectometry (TDR)
        2. 9.3.16.2 Fast Link-Drop Functionality
      17. 9.3.17 LED and GPIO Configuration
    4. 9.4 Programming
      1. 9.4.1 Hardware Bootstraps Configuration
        1. 9.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 9.4.1.1.1 Bootstraps for PHY Address
        2. 9.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 9.4.1.2.1 Bootstraps for PHY Address
    5. 9.5 Register Maps
      1. 9.5.1 DP83826 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 10.2.2 Transformer Recommendations
      3. 10.2.3 Capacitive DC Blocking
      4. 10.2.4 Design Requirements
        1. 10.2.4.1 Clock Requirements
          1. 10.2.4.1.1 Oscillator
          2. 10.2.4.1.2 Crystal
      5. 10.2.5 Detailed Design Procedure
        1. 10.2.5.1 MII Layout Guidelines
        2. 10.2.5.2 RMII Layout Guidelines
        3. 10.2.5.3 MDI Layout Guidelines
      6. 10.2.6 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
        1. 12.1.5.1 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision F (November 2022) to Revision G (July 2023)

  • Adjusted tables to clarify accurate representation of device performanceGo
  • Corrected pin 16 reset state. Clarified pin 31 functionality.Go
  • Adjusted pin 20 and 21 descriptionGo
  • Clarified how to disable CLKOUTGo
  • Adjusted hyperlink to app noteGo
  • Revised description of which configurations are used to control respective mechanisms of FLD. Simplified table description.Go
  • Updated flowchartGo
  • Clarified Strap6 and Strap1 are both latched at POR onlyGo
  • Consolidated and clarified MAC Mode Selection Strap TableGo
  • Updated device registersGo
  • Updated linksGo

Changes from Revision E (February 2022) to Revision F (November 2022)

  • Corrected Reset states for RX_D3, LED0Go
  • Updated thermal metricGo
  • Adjusted Power-Up Timing (Power Sequencing) graphic Go
  • Adjusted RMII Repeater Mode: Master-Slave and RMII Repeater Mode: Slave-Slave graphics Go
  • Clarified MDIO pullup resistor valuesGo
  • Changed Rlo strap for internal PU pin to 1.5kΩ. Added recommended tolerance for resistor values.Go
  • Added Enhanced Bootstrap Flowchart graphicGo
  • Corrected Strap0 default and functionality in Enhanced ModeGo
  • Updated device registersGo
  • Adjusted location of Transformer Recommendations Go

Changes from Revision D (October 2020) to Revision E (February 2022)

  • Pin 31 default is changed to LED1, added odd nibble detection and FLD detection mechanisms in hardware bootstrap differences tableGo
  • Added TX_ER to pin 28Go
  • Pin 31 default is changed to LED1Go
  • Pin 31 default is changed to LED1, updated pin 16 and pin 31 to PUGo
  • Added fast link drop modes table, updated description for fast link drop functionality in Included specification for the different defaults between enhanced and basic mode, added strap8 descriptionGo
  • Added description that LED1/0 are autopolarity (enhanced), active low by default (basic)Go
  • Added odd nibble detection table, added strap7 and strap1 interaction to MII MAC mode strap table, added signal energy alternate function to strap8Go
  • Pin 31 default is changed to LED1, pin 16 default changed to half duplexGo
  • TPI network cap updatesGo

Changes from Revision C (July 2020) to Revision D (October 2020)

  • Updated Electrical Characteristics table.Go
  • Added sectionGo

Changes from Revision B (March 2020) to Revision C (July 2020)

  • Added link to SNLA338 application noteGo
  • Added link to SNLA338Go
  • Energy Efficient Ethernet sectionGo
  • EEE Overview sectionGo
  • EEE Negotiation sectionGo
  • Added EEE for Legacy MACs Not Supporting 802.3az sectionGo
  • Updated device registersGo
  • Added link to SNLA338 application noteGo

Changes from Revision A (February 2020) to Revision B (March 2020)

  • Added DP83826I temperature range in Electrical Section alsoGo
  • Added DP83826I to Device Family Information tableGo

Changes from Revision * (January 2020) to Revision A (February 2020)

  • Added link to DP83826EVM User's Guide Go
  • Deleted pin 18 from Table 5-2 Go
  • Changed ENHANCED Mode pin map and pin functions table to match pin namesGo
  • Changed BASIC Mode pin map and pin functions table to match pin namesGo
  • Deleted "This pin can be configured to RX_DV in RMII mode to enable RMII Repeater Mode." from Pin Functions (BASIC Mode)Go
  • Added the 100BASE-TX Transmit Latency Timing graphic Go
  • Added the 100BASE-TX Receive Latency Timing graphic Go
  • Added steps to disable CLKOUT via register configuration in Section 9.3.8 Go
  • Deleted mentions of "clause 45" from Section 9.3.11 and Section 9.3.11.1 Go
  • Deleted "Analog Loopback requires 100-Ω terminations across pins #1 and #2 as well as 100-Ω terminations across pins #3 and #6 at the RJ45." from Section 9.3.14.5 Go
  • Added row for RMII slave mode configuration in Table 9-15 Go