SLVSFL8 July   2021 DRV8770

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gate Drivers
        1. 7.3.1.1 Gate Drive Timings
          1. 7.3.1.1.1 Propagation Delay
          2. 7.3.1.1.2 Deadtime and Cross-Conduction Prevention
        2. 7.3.1.2 Mode (Inverting and non-inverting INLx)
      2. 7.3.2 Pin Diagrams
      3. 7.3.3 Gate Driver Protective Circuits
        1. 7.3.3.1 VBSTx Undervoltage Lockout (BSTUV)
        2. 7.3.3.2 GVDD Undervoltage Lockout (GVDDUV)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Example
    2. 10.2 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1.2 Mode (Inverting and non-inverting INLx)

The DRV8770 has flexibility of accepting different kind of inputs on INLx. In the QFN (RGE) package variant, the MODE pin provides option of GLx output inverted or non-inverted compared to polarity of signal on INLx pin. When the MODE pin is left floating, INLx is configured to be in non-inverting mode and GLx output is in phase with INLx (see Figure 7-3). When MODE pin is connected to GVDD, GLx output is out of phase with inputs (see Figure 7-4). The TSSOP (PW) package variant does not have a MODE pin, so the INLx pins are inverted by default.

GUID-4C02EC0E-172D-4675-A767-B15581777459-low.gif Figure 7-3 Non-Inverted INLx inputs (MODE = floating)
GUID-77F99BB3-45D7-4F3F-BAA5-AC9A8CE7CEDE-low.gif Figure 7-4 Inverted INLx inputs (MODE = GVDD or TSSOP package variant)

Table 7-1 shows the states of the gate drivers and FET half bridge when MODE = floating.

Table 7-1 Logic table when MODE = floating
INHx INLx GHx GLx Half Bridge State
0 0 L L Z, FETs disabled
0 1 L H L, low-side FET enabled
1 0 H L H, high-side FET enabled
1 1 L L Z, invalid state

Table 7-2 shows the states of the gate drivers and FET half bridge for the inverted mode (MODE = GVDD or the default mode of the TSSOP package). In this mode, the INHx and INLx pins can be tied together to reduce the number of control signals from a microcontroller, as shown in Table 7-3. In this configuration, the device controls the deadtime as described in Section 7.3.1.1.2.

Table 7-2 Logic table when MODE = GVDD or TSSOP package variant
INHx INLx GHx GLx Half Bridge State
0 0 L H L, low-side FET enabled
0 1 L L Z, FETs disabled
1 0 L L Z, invalid state
1 1 H L H, high-side FET enabled
Table 7-3 Logic table when INHx = INLx for MODE = GVDD or TSSOP package variant
INHx = INLx GHx GLx Half Bridge State
0 L H L, low-side FET enabled
1 H L H, high-side FET enabled