7.3.1 High-Speed Forward Channel Data Transfer

The high-speed forward channel (HS_FC) is composed of 35 bits of data containing RGB data, sync signals, HDCP, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 12 illustrates the serial stream per PCLK cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized, balanced and scrambled.

Figure 12. FPD-Link III Serial Stream

The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975-Gbps maximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps minimum.

7.3.2 Low-Speed Back Channel Data Transfer

The low-speed backward channel (LS_BC) of the DS90UH926Q-Q1 provides bidirectional communication between the display and host processor. The information is carried back from the Deserializer to the Serializer per serial symbol. The back channel control data is transferred over the single serial link along with the high-speed forward data, DC balance coding, and embedded clock information. This architecture provides a backward path across the serial link together with a high-speed forward channel. The back channel contains the I2C, HDCP, CRC and 4 bits of standard GPIO information with 10-Mbps line rate.

7.3.3 Backward Compatible Mode

The DS90UH926Q-Q1 is also backward-compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers with 15- to 65-MHz pixel clock frequencies supported. It receives 28 bits of data over a single serial FPD-Link II pair operating at the line rate of 420 Mbps to 1.82 Gbps. This backward-compatible mode is provided through the MODE_SEL pin (Table 9) or the configuration register (Table 11). When backward-compatible mode = ON, set LFMODE = 0.

7.3.4 Input Equalization Gain

FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces the medium-induced deterministic jitter. It equalizes up to 10 meter STP cables with 3 connection breaks at maximum serialized stream payload rate of 2.975 Gbps.

7.3.5 Common-Mode Filter Pin (CMF)

The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability. A 0.1-μF capacitor has to be connected to this pin to Ground.

7.3.6 Video Control Signal Filter

When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions:

• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low-frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency noise on the control signals. See Figure 13.

Figure 13. Video Control Signal Filter Waveform

7.3.7 EMI Reduction Features

7.3.7.1 Spread Spectrum Clock Generation (SSCG)

The DS90UH926Q-Q1 provides an internally-generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.5% (5% total) at up to 100-kHz modulations are available. This feature may be controlled by register. See Table 1, Table 2 and Table 11. Do not enable the SSCG feature if the source PCLK into the SER has a clock with spread spectrum already.

Figure 14. SSCG Waveform

Table 1. SSCG Configuration
LFMODE = L (15 to 85 MHz)

SSCG CONFIGURATION (0x2C) LFMODE = L (15 to 85 MHz)			SPREAD SPECTRUM OUTPUT
SSC[2]	SSC[1]	SSC[0]	Fdev (%)	Fmod (kHz)
L	L	L	±0.9	PCLK / 2168
L	L	H	±1.2
L	H	L	±1.9
L	H	H	±2.5
H	L	L	±0.7	PCLK / 1300
H	L	H	±1.3
H	H	L	±2.0
H	H	H	±2.5

Table 2. SSCG Configuration
LFMODE = H (5 to < 15 MHz)

SSCG CONFIGURATION (0x2C) LFMODE = H (5 to <15 MHz)			SPREAD SPECTRUM OUTPUT
SSC[2]	SSC[1]	SSC[0]	Fdev (%)	Fmod (kHz)
L	L	L	±0.5	PCLK / 628
L	L	H	±1.3
L	H	L	±1.8
L	H	H	±2.5
H	L	L	±0.7	PCLK / 388
H	L	H	±1.2
H	H	L	±2
H	H	H	±2.5

7.3.8 Enhanced Progressive Turnon (EPTO)

The deserializer LVCMOS parallel outputs timing are delayed. Groups of 8-bit R, G and B outputs switch in a different time. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI.

7.3.9 LVCMOS VDDIO Option

The deserializer parallel bus can operate with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.

7.3.10 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the host or through the V_DDIO, where V_DDIO = 3 to 3.6 V or V_DD33. To save power disable the link when the display is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after V_DD33 and V_DDIO have reached final levels; no external components are required. In the case of driven by the V_DDIO = 3 to 3.6 V or V_DD33 directly, a 10 kΩ resistor to the V_DDIO = 3 to 3.6 V or V_DD33 , and a > 10 µF capacitor to the ground are required (See Figure 24).

7.3.11 Stop Stream Sleep

The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer will then lock to the incoming signal and recover the data.

7.3.12 Serial Link Fault Detect

The serial link fault detection is able to detect any of following 7 conditions

1. cable open
2. + to - short
3. + short to GND
4. - short to GND
5. + short to battery
6. - short to battery
7. Cable is linked incorrectly

If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on the Serial Control Bus Register bit 0 of address 0x1C Table 11. The link errors can be monitored though Link Error Count of the Serial Control Bus Register bit [4:0] of address 0x41 Table 11.

7.3.13 Oscillator Output

The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by register Address 0x02, bit 5 (OSC Clock Enable). See Table 11.

7.3.14 Pixel Clock Edge Select (RFB)

The RFB determines the edge that the data is strobed on. If RFB is High (‘1’), output data is strobed on the Rising edge of the PCLK. If RFB is Low (‘0’), data is strobed on the Falling edge of the PCLK. This allows for inter-operability with downstream devices. The deserializer output does not need to use the same edge as the Ser input. This feature may be controlled by register. See Table 11.

7.3.15 Built In Self Test (BIST)

An optional At-Speed, Built-In Self Test (BIST) feature supports the testing of the high speed serial link and the low- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. The BIST is not available in backwards-compatible mode.

7.3.15.1 BIST Configuration and Status

The BIST mode is enabled at the deserializer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) or configuration register (Table 11) through the deserializer. When LFMODE = 0, the pin based configuration defaults to external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the desired OSC frequency (default 33 MHz or 25 MHz) through the register bit. When LFMODE = 1, the pin based configuration defaults to external PCLK or 12.5 MHz MHz internal Oscillator clock (OSC) frequency.

When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through the Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1- to 35-bit errors.

The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset (new BIST test or Power Down). A High on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If the connection of the serial link is broken, then the link error count is shown in the register. When the PLL of the deserializer is locked or unlocked, the lock status can be read in the register. See Table 11.

7.3.15.1.1 Sample BIST Sequence

See Figure 15 for the BIST mode flow diagram.

1. For the DS90UH925Q-Q1 and DS90UH926Q-Q1 FPD-Link III chipset, BIST Mode is enabled through the BISTEN pin of DS90UH926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through BISTC pin.
2. The DS90UH925Q-Q1 serializer is woken up through the back channel if it is not already on. The all zero pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.
3. To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
4. The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 16 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal condition enhancements ( Rx Equalization).

Figure 15. BIST Mode Flow Diagram

7.3.15.2 Forward-Channel and Back-Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zero pattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link to the deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. The deserializer then outputs a SSO pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream as indicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. The register is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, the functional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of last BIST run until it clears or enters BIST mode again.

Figure 16. BIST Waveforms

7.3.16 Image Enhancement Features

Several image enhancement features are provided. White balance LUTs allow the user to define and target the color temperature of the display. Adaptive Hi-FRC dithering enables the presentation of “true-color” images on an 18–bit color display.

7.3.16.1 White Balance

The White Balance feature enables similar display appearance when using LCDs from different vendors. It compensates for native color temperature of the display, and adjusts relative intensities of R, G, B to maintain specified color temperature. Programmable control registers are used to define the contents of three LUTs (8-bit color value for Red, Green and Blue) for the white balance feature. The LUTs map input RGB values to new output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8 bits per entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. Calibrated values are loaded into registers through the I2C interface (deserializer is a slave device). This feature may also be applied to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is enabled and configured through that serial control bus register.

7.3.16.1.1 LUT Contents

The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3 tables. Unused bits - LSBs -shall be set to 0 by the user.

When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique 8-bit entries. The 8-bit white balanced data is then available at the output of the DS90UH926Q-Q1 deserializer, and driven to the display.

When 18-bit (666) input data is being driven to an 18-bit display, the white balance feature may be used in one of two ways. First, simply load each LUT with 256, 8-bit entries. Each 8-bit entry is a 6-bit value (6 MSBs) with the 2 LSBs set to 00. Thus as total of 64 unique 6-bit white balance output values are available for each color (R, G and B). The 6-bit white balanced data is available at the output of the DS90UH926Q-Q1 deserializer, and driven directly to the display.

Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the user must configure the DS90UH926Q-Q1 to enable the FRC2 function.

Examples of the three types of LUT configurations described are shown in Figure 17

7.3.16.1.2 Enabling White Balance

The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be followed by the user.

To initialize white balance after power-on (Table 3):

1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance.

By default, the LUT data may not be reloaded after initialization at power-on.

An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This option may only be used after enabling the white balance reload feature through the associated serial control bus register. In this mode the LUTs may be reloaded by the master controller through the I2C. This provides the user with the flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT values. The host controller loads the updated LUT values through the serial bus interface. There is no need to disable the white balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be seamless - no interruption of displayed data.

It is important to note that initial loading of LUT values requires that all three LUTs be loaded sequentially. When reloading, partial LUT updates may be made.

Figure 17. White Balance LUT Configurations

Table 3. White Balance Register Table

PAGE	ADD (dec)	ADD (hex)	REGISTER NAME	BITS	ACCESS	DEFAULT (hex)	FUNCTION	DESCRIPTION
0	42	0x2A	White Balance Control	7:6	RW	0x00	Page Setting	00: Configuration Registers 01: Red LUT 10: Green LUT 11: Blue LUT
				5	RW		White Balance Enable	0: White Balance Disable 1: White Balance Enable
				4	RW			0: Reload Disable 1: Reload Enable
				3:0				Reserved
1	0 – 255	00 – FF	White Balance Red LUT	FF:0	RW	N/A	Red LUT	256 8–bit entries to be applied to the Red subpixel data
2	0 – 255	00 – FF	White Balance Green LUT	FF:0	RW	N/A	Green LUT	256 8–bit entries to be applied to the Green subpixel data
3	0 – 255	00 – FF	White Balance Blue LUT	FF:0	RW	N/A	Blue LUT	256 8–bit entries to be applied to the Blue subpixel data

7.3.16.2 Adaptive HI-FRC Dithering

The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits per subpixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full (16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is enabled through the serial control bus register.

Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT that is calibrated for an 18-bit data source. The second FRC block, FRC2, follows the white balance block and is intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a 24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data.

For proper operation of the FRC dithering feature, the user must provide a description of the display timing control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active polarity of the timing control signals. All this information is entered to DS90UH926Q-Q1 control registers through the serial bus interface.

Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off sub-pixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level transitions. Three algorithms are defined to support these critical transitions.

An example of the default dithering algorithm is illustrated in Figure 18. The 1 or 0 value shown in the table describes whether the 6-bit value is increased by 1 (1) or left unchanged (0). In this case, the 3 truncated LSBs are 001.

Figure 18. Default FRC Algorithm

Table 4. Recommended FRC Settings

SOURCE	WHITE BALANCE LUT	DISPLAY	FRC1	FRC2
24–bit	24–bit	24–bit	Disabled	Disabled
24–bit	24–bit	18–bit	Disabled	Enabled
24–bit	18–bit	18–bit	Enabled	Disabled
18–bit	24–bit	24–bit	Disabled	Disabled
18–bit	24–bit	18–bit	Disabled	Enabled
18–bit	18–bit	18–bit	Disabled	Disabled

7.3.17 Internal Pattern Generation

The DS90UH926Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to AN-2198 Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices (SNLA132).

7.3.18 I2S Receiving

In normal 24-bit RGB operation mode, the DS90UH926Q-Q1 provides up to 3-bit of I2S. They are I2S_CLK, I2S_WC and I2S_DA, as well as the Master I2S Clock (MCLK). The audio is received through the forward video frame, or can be configured to receive during video blanking periods. A jitter cleaning feature reduces I2S_CLK output jitter to +/- 2ns. The encrypted and packetized audio information is received during the video blanking periods along with specific information about the clock frequency. The bit rates of any I2S input bits must maintain one fourth of the PCLK rate. The audio decryption is supported per HDCP v1.3.

7.3.19 Interrupt Pin: Functional Description and Usage (INTB)

1. On DS90UH925Q-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UH926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UH925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .
5. A read to HDCP_ISR will clear the interrupt at the DS90UH925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the INTB_IN (pin 16) on the DS90UH926Q-Q1. The system is now ready to return to step (1) at next falling edge of INTB_IN.

7.3.20 GPIO[3:0] and GPO_REG[8:4]

In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UH926Q-Q1 can be used as the general purpose IOs GPIO[3:0] in either forward channel (Outputs) or back channel (Inputs) application.

7.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State Select (OSS_SEL)

When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW (depending on the value of the OEN setting). After the DS90UH926Q-Q1 completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and PCLK outputs. The State of the outputs are based on the OEN and OSS_SEL setting (Table 8) or register bit (Table 11). See Figure 7.

7.4.2 Low Frequency Optimization (LFMODE)

The LFMODE is set through a register (Table 11) or MODE_SEL Pin 24 (Table 9). It controls the operating frequency of the deserializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High, the PCLK frequency is between 5 MHz and <15 MHz. Please note: when the device LFMODE is changed, a PDB reset is required.

7.4.3 Configuration Select (MODE_SEL)

Configuration of the device may be done through the MODE_SEL input pin, or through the configuration register bit. A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (V_R4) and V_DD33 to select one of the other 10 possible selected modes. See Figure 19 and Table 9.

Figure 19. MODE_SEL Connection Diagram

7.4.4 HDCP Repeater

When DS90UH925Q-Q1 and DS90UH926Q-Q1 are configured as the HDCP Repeater application, it provides a mechanism to extend HDCP transmission over multiple links to multiple display devices. This repeater application provides a mechanism to authenticate all HDCP Receivers in the system and distribute protected content to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification.

In this document, the DS90UH925Q-Q1 is referred to as the HDCP Transmitter or transmit port (TX), and the DS90UH926Q-Q1 is referred to as the HDCP Receiver (RX). Figure 20 shows the maximum configuration supported for HDCP Repeater implementations using the DS90UH925Q-Q1 (TX) and DS90UH926Q-Q1 (RX). Two levels of HDCP Repeaters are supported with a maximum of three HDCP Transmitters per HDCP Receiver.

Figure 20. HDCP Maximum Repeater Application

To support HDCP Repeater operation, the DS90UH926Q-Q1 Deserializer includes the ability to control the downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV list to the upstream HDCP Transmitter. An I2C master within the DS90UH926Q-Q1 communicates with the I2C slave within the DS90UH925Q-Q1 Serializer. The DS90UH925Q-Q1 Serializer handles authenticating with a downstream HDCP Receiver and makes status available through the I2C interface. The DS90UH926Q-Q1 monitors the transmit port status for each DS90UH925Q-Q1 and reads downstream KSV and KSV list values from the DS90UH925Q-Q1.

In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementation includes two other interfaces. A parallel LVCMOS interface provides the unencrypted video data in 24-bit RGB format and includes the DE/VS/HS control signals. In addition to providing the RGB video data, the parallel LVCMOS interface communicates control information and packetized audio data during video blanking intervals. A separate I2S audio interface may optionally be used to send I2S audio data between the HDCP Receiver and HDCP Transmitter in place of using the packetized audio over the parallel LVCMOS interface. All audio and video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter.

Figure 21 provides more detailed block diagram of a 1:2 HDCP repeater configuration.

Figure 21. HDCP 1:2 Repeater Configuration

7.4.4.1 Repeater Connections

The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP Transmitter Figure 22.

1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to V_DD33 with 4.7-kΩ resistors
3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.
4. IDx pin – Each HDCP Transmitter and Receiver must have an unique I2C address.
5. MODE_SEL pin – All HDCP Transmitter and Receiver must be set into the Repeater Mode.
6. Interrupt pin– Connect DS90UH926Q-Q1 INTB_IN pin to DS90UH925Q-Q1 INTB pin. The signal must be pulled up to V_DDIO.

Figure 22. HDCP Repeater Connection Diagram

7.5.1 Serial Control Bus

The DS90UH926Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple deserializer devices may share the serial control bus since 16 device addresses are supported. Device address is set through the R₁ and R₂ values on IDx pin. See Figure 23.

The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input / Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to V_DD33. For most applications a 4.7 kΩ pull-up resistor to V_DD33 may be used. The resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low.

Figure 23. Serial Control Bus Connection

The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (V_R2) and V_DD33 to select one of the other 16 possible addresses. See Table 10

Table 11. Serial Control Bus Registers