8.3.1 Comparator

The INA203-Q1 incorporates two open-drain comparators. These comparators typically have 2 mV of offset and a 1.3-μs (typical) response time. The output of Comparator 1 latches and is reset through the CMP1 RESET pin, as shown in Figure 26.

The INA203-Q1 device includes additional features for comparator functions. The comparator reference voltage of both Comparator 1 and Comparator 2 can be overridden by external inputs for increased design flexibility. Comparator 2 has a programmable delay.

Figure 26. Comparator Latching Capability

8.3.2 Comparator Delay

The Comparator 2 programmable delay is controlled by a capacitor connected to the CMP2 Delay Pin; see Figure 30. The capacitor value (in μF) is selected by using Equation 1:

Equation 1.

A simplified version of the delay circuit for Comparator 2 is shown in Figure 27. The delay comparator consists of two comparator stages with the delay between them.

Using an initial assumption that the U1 output is low, I1 is on, then U2 +IN is zero. If U1 goes high, I2 supplies 120 nA to C_DELAY. The voltage at U2 +IN begins to ramp toward a 0.6-V threshold. When the voltage crosses this threshold, the U2 output goes high while the voltage at U2 +IN continues to ramp up to a maximum of 1.2 V when given sufficient time (twice the value of the delay specified for C_DELAY). This entire sequence is reversed when the comparator outputs go low, so that returning to low exhibits the same delay.

Figure 27. Simplified Model of The Comparator 2 Delay Circuit

It is important to note the behavior of the Comparator 2 when the events at the inputs occur more rapidly than the set delay timeout. For example, when the U1 output goes high (turning on I2), but returns low (turning I1 back on) prior to reaching the 0.6 V transition for U2. The voltage at U2 +IN ramps back down at a rate determined by the value of C_DELAY, and only returns to zero if given sufficient time.

In essence, when analyzing Comparator 2 for behavior with events more rapid than its delay setting, use the model shown in Figure 27.

8.3.3 Comparator Maximum Input Voltage Range

The maximum voltage at the comparator input for normal operation is up to (V_S) – 1.5 V. There are special considerations when overdriving the reference inputs (pins 3 and 6). Driving either or both inputs high enough to drive 1 mA back into the reference introduces errors into the reference. Figure 28 shows the basic input structure. A general guideline is to limit the voltage on both inputs to a total of 20 V. The exact limit depends on the available voltage and whether either or both inputs are subject to the large voltage. When making this determination, consider the 20 kΩ from each input back to the comparator. Figure 29 shows the maximum input voltage that avoids creating a reference error when driving both inputs (an equivalent resistance back into the reference of 10 kΩ).

Figure 28. Limit Current Into Reference ≤ 1 mA

Figure 29. Overdriving Comparator Inputs Without Generating a Reference Error

8.3.4 Reference

The INA203-Q1 include an internal voltage reference that has a load regulation of 0.4 mV/mA (typical), and not more than 100 ppm/°C of drift. The device allows external access to reference voltages, where voltages of 1.2 V and 0.6 V are both available. Output current versus output voltage is illustrated in the Typical Characteristics section.

8.3.5 Output Voltage Range

The output of the INA203-Q1 is accurate within the output voltage swing range set by the power-supply pin, V_S. Given the device gain of 20, where a 250 mV full-scale input from the shunt resistor requires an output voltage swing of +5 V, and a power-supply voltage sufficient to achieve +5 V on the output.