SNVSB12B November   2017  – May 2021 LM73605-Q1 , LM73606-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Synchronous Step-Down Regulator
      2. 8.3.2  Auto Mode and FPWM Mode
      3. 8.3.3  Fixed-Frequency Peak Current-Mode Control
      4. 8.3.4  Adjustable Output Voltage
      5. 8.3.5  Enable and UVLO
      6. 8.3.6  Internal LDO, VCC_UVLO, and BIAS Input
      7. 8.3.7  Soft Start and Voltage Tracking
      8. 8.3.8  Adjustable Switching Frequency
      9. 8.3.9  Frequency Synchronization and Mode Setting
      10. 8.3.10 Internal Compensation and CFF
      11. 8.3.11 Bootstrap Capacitor and VBOOT-UVLO
      12. 8.3.12 Power-Good and Overvoltage Protection
      13. 8.3.13 Overcurrent and Short-Circuit Protection
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 DCM Mode
        3. 8.4.3.3 PFM Mode
        4. 8.4.3.4 Fault Protection Mode
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Layout For EMI Reduction
      2. 9.1.2 Ground Plane
      3. 9.1.3 Optimize Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, VIN = 12 V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY VOLTAGE (PVIN PINS)
VINOperating input voltage range3.536V
ISDShutdown quiescent current; measured at VIN pin(1)VEN = 0 V
TJ = 25℃
0.810µA
IQ_NONSWOperating quiescent current from VIN (non-switching)VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external0.612µA
ENABLE (EN PIN)
VEN_VCC_HEnable input high level for VCC outputVEN rising1.15V
VEN_VCC_LEnable input low level for VCC outputVEN falling0.3V
VEN_VOUT_HEnable input high level for VOUTVEN rising1.141.1961.25V
VEN_VOUT_HYSEnable input hysteresis for VOUTVEN falling hysteresis–100mV
ILKG_ENEnable input leakage currentVEN = 2 V1.4200nA
INTERNAL LDO (VCC PIN, BIAS PIN)
VCCInternal VCC voltagePWM operation3.27V
PFM operation3.1V
VCC_UVLOInternal VCC undervoltage lockoutVCC rising2.963.143.27V
VCC falling hysteresis–605mV
VBIAS_ONInput changeoverVBIAS rising3.093.25V
VBIAS falling hysteresis–63mV
IBIAS_NONSWOperating quiescent current from external VBIAS (non-switching)VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external2150µA
VOLTAGE REFERENCE (FB PIN)
VFBFeedback voltagePWM mode0.9871.0061.017V
ILKG_FBInput leakage current at FB pinVFB = 1 V0.260nA
HIGH SIDE DRIVER (CBOOT PIN)
VCBOOT_UVLOCBOOT - SW undervoltage lockout1.62.22.7V
CURRENT LIMITS AND HICCUP
IHS_LIMITShort-circuit, high-side current limit(2)LM73605-Q167.38.35A
LM73606-Q17.48.79.85
ILS_LIMITLow-side current limit(2)LM73605-Q14.795.56.1A
LM73606-Q15.86.67.25
INEG_LIMITNegative current limitLM73605-Q1–5A
LM73606-Q1–6
VHICCUPHiccup threshold on FB pin0.360.40.44V
IL_ZCZero cross-current limit0.06A
SOFT START (SS/TRK PIN)
ISSCSoft-start charge current1.822.2µA
RSSDSoft-start discharge resistanceUVLO, TSD, OCP, or EN = 01
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION
VPGOOD_OVPower-good overvoltage threshold% of FB voltage106%110%113%
VPGOOD_UVPower-good undervoltage threshold% of FB voltage86%90%93%
VPGOOD_HYSPower-good hysteresis% of FB voltage1.2%
VPGOOD_VALIDMinimum input voltage for proper PGOOD function50-µA pullup to PGOOD pin, VEN = 0 V, TJ = 25°C1.32V
RPGOODPower-good ON-resistanceVEN = 2.5V40100Ω
VEN = 0 V3090
MOSFETS
RDS_ON_HS(3)High-side MOSFET ON-resistanceIOUT  = 1 A, VBIAS = VOUT = 3.3 V5390mΩ
RDS_ON_LS(3)Low-side MOSFET ON-resistanceIOUT  = 1 A, VBIAS = VOUT = 3.3 V3155mΩ
THERMAL SHUTDOWN
TSD(4)Thermal shutdown thresholdShutdown threshold160°C
Recovery threshold135°C
Shutdown current includes leakage current of the switching transistors.
This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and drivers, the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower.
Measured at pins
Ensured by design