SNAS880 December   2024 LMK3C0105

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Digital State Machine
        3. 7.4.2.3 Spread-Spectrum Clocking
        4. 7.4.2.4 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
        2. 7.4.3.2 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Separate Output Enable
        4. 7.4.4.4 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1804]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA7]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x5D1F]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3000/0x1000]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 8.1.14 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RER|16
Thermal pad, mechanical data (Package|Pins)

9.2.4 Example: Changing Output Frequency

If the user wants to change the output from 25MHz LVCMOS on OUTA, OUTB, and OUTD to 24MHz differential LVCMOS clocks on all outputs, the following example details this process. The value of the BAWFREQ_OFFSET_FIXEDLUT field for this example is 0x3701. The steps for changing the frequency are as follows:

  1. Determine the BAW frequency of the device. This is critical for all following calculations. From Equation 4, if BAWFREQ_OFFSET_FIXEDLUT is 0x3701, then the BAW frequency of this device is approximately 2471.446441856MHz.
  2. Determine the channel divider settings and required FOD frequency. If the output frequency is 24MHz, and the range of the FODs is from 100MHz to 400MHz, then a channel divider value of at least 5 is required to generate the output. As there is not a divide by 5 option, and REF_CLK must also have a clock (see CH0_DIV, CH1_DIV, and REF_CLK_DIV), a divide by 8 is required. From here, 24MHz times 8 yields an FOD output frequency of 192MHz. If OUTC/OUTD were a different frequency, then using FOD1 can be required if both frequencies cannot be generated by dividing down from the same FOD frequency.
  3. Set the FOD divide values. Use Equation 1 to calculate the integer divide value FOD0_N_DIV = floor(2471.446441856/192) = 12. From Equation 2, the numerator divide value FOD0_NUM = int(((2471.446441856/192) - 12) x 224) = 14631693
  4. Write the desired settings to the device registers. This includes the divider settings listed above, as well as the output driver settings. Follow the procedure outlined in Figure 7-4:
    1. Set PDN = 1.
    2. Set FOD0_N_DIV = 12 and FOD0_NUM = 14631693.
    3. Set CH0_DIV, and REF_CLK_DIV to divide by 8 (by default, OUTCD_CH_SEL is set to select Channel Divider 0).
    4. Set OUTAB_FMT and OUTCD_FMT to select in-phase LVCMOS as the output format.
    5. Set REF_CTRL_PIN_FUNC to output REF_CLK.
    6. Set OTP_AUTOLOAD_DIS to 1 (disable the OTP Page 0 autoload feature).
    7. Set DIG_CLK_N_DIV = 2 to set the digital state machine clock to 48MHz, based on Equation 9
    8. Set PDN = 0

The time required for the frequency change to take affect is typically on the order of 1ms between issuing PDN = 0 and the output clocks starting at the desired frequency.