8.3.2.1 PWM Input Duty Cycle

With PWM input pin duty cycle control the output PWM is controlled by PWM input duty cycle. PWM detector block measures the duty cycle in the PWM pin and uses this 13-bit value to generate the output PWM. Output PWM can have different frequency than input in this mode and also phase shift PWM mode can be used. Slope is effective in this mode. PWM input resolution is defined by the input PWM clock frequency.

8.3.2.2 Brightness Register Control

With brightness register control the output PWM is controlled with 8-bit resolution <BRT7:0> register bits. Phase shift scheme can be used with this, and the output PWM frequency can be freely selected. Slope is effective in this mode.

8.3.2.3 PWM Direct Control

With PWM direct control the output PWM directly follows the input PWM. Due to the internal logic structure the input is anyway clocked with the 5 MHz clock or the PLL clock. PSPWM mode is not possible in this mode. Slope is not effective in this mode.

8.3.2.4 PWM Calculation Data Flow

Figure 9 shows the PWM calculation data flow. In PWM direct control mode most of the blocks are bypassed, and this flow chart does not apply.

Figure 9. PWM Calculation Data Flow

8.3.2.5 PWM Detector

The PWM detector block measures the duty cycle of the input PWM signal. Resolution depends on the input signal frequency. Hysteresis selection sets the minimum allowable change to the input. If smaller change is detected, it is ignored. With hysteresis the constant changing between two brightness values is avoided if there is small jitter in the input signal.

8.3.2.6 Brightness Control

Brightness control block gets 13-bit value from the PWM detector, 12-bit value from the temperature sensor, and also 8-bit value from the brightness register. <BRT_MODE[1:0]> selects whether to use PWM input duty cycle value or the brightness register value as described earlier. Based on the temperature sensor value the duty cycle is reduced if the temperature has reached the temperature limit set to the <TEMP_LIM[1:0]> EEPROM bits.

8.3.2.7 Resolution Selector

Resolution selector takes the necessary MSB bits from the input data to match the output resolution. For example if 11-bit resolution is used for output, then 11 MSB bits are selected from the input.

8.3.2.8 Sloper

Sloper makes the smooth transition from one brightness value to another. Slope time can be adjusted from 0 to 500 ms with <SLOPE[3:0]> EEPROM bits. The sloper output is 16-bit value.

8.3.2.9 PWM Comparator

The PWM counter clocks the PWM comparator based on the duty cycle value. Output of the PWM comparator controls directly the LED drivers. If PSPWM mode is used, then the signal to each LED output is delayed certain amount.

8.3.2.10 Current Setting

Maximum current of the LED outputs is controlled with CURRENT[7:0] EEPROM register bits linearly from 0 to 30 mA. If <EN_I_RES> = 1 the maximum LED output current can be scaled also with external resistor, R_ISET. R_ISET controls the LED current as follows:

Equation 1.

Default value for CURRENT[7:0] = 7Fh (127d). Therefore, the output current can be calculated as follows:

Equation 2.

For example, if a 16-kΩ R_ISET resistor is used, then the LED maximum current is 23 mA.

8.3.2.11 PWM Frequency Setting

PWM frequency is selected with PWM_FREQ[4:0] EEPROM register. If PLL clock frequency multiplication is used, it affects the output PWM frequency as well. <PWM_RESOLUTION[1:0]> EEPROM bits select the PLL output frequency and hence the PWM frequency and resolution. PWM resolution setting affects the PLL clock frequency (5 MHz to 40 MHz). Highlighted frequencies with boldface can be selected also with external resistor R_FSET. To activate R_FSET frequency selection the <EN_F_RES> EEPROM bit must be 1.

R_FSET resistance values with corresponding PWM frequencies:

8.3.2.12 Phase Shift PWM (PSPWM) Scheme

The PSPWM scheme allows delaying the time when each LED output is active. When the LED output are not activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the ripple seen on the boost output and allows smaller output capacitors. Reduced ripple also reduces the output ceramic capacitor audible ringing. PSPWM scheme also increases the load frequency seen on boost output by x4 and therefore transfers the possible audible noise to so high frequency that human ear cannot hear it.

Description of the PSPWM mode is seen on the following diagram. PSPWM mode is enabled by setting <EN_PSPWM> EEPROM bit to 1. Shift time is the delay between outputs and it is defined as 1 / (f_PWM x 4). If the <EN_PSPWM> bit is 0, then the delay is 0 and all outputs are active simultaneously.

Figure 10. PSPWM Mode

8.3.2.13 Slope

Slope time can be programmed with EEPROM bits <SLOPE[3:0]> from 0 to 500 ms. The same slope time is used for sloping up and down. Advanced slope makes brightness changes smooth for eye.

Figure 11. Sloper Operation

8.3.2.14 Driver Headroom Control

Driver headroom can be controlled with <DRV_HEADR[2:0]> EEPROM bits. Driver headroom control sets the minimum threshold for the voltage over the LED output which has the smallest driver headroom and controls the boost output voltage accordingly. Boost output voltage step size is 125 mV. The LED output which has the smallest forward voltage is the one which has highest V_F across the LEDs. The strings with highest forward voltage is detected automatically. To achieve best possible efficiency smallest possible headroom voltage should be selected. If there is high variation between LED strings, the headroom can be raised slightly to prevent any visual artifacts.

8.3.3.1 Operation

The LP8551 boost DC/DC converter generates a 10-V to 40-V supply voltage for the LEDs from 2.7-V to 22-V input voltage. The output voltage can be controlled either with EEPROM register bits <VBOOST[4:0]> or automatic adaptive voltage control can be used. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The topology of the magnetic boost converter is called CPM (current programmed mode) control, where the inductor current is measured and controlled with the feedback. Switching frequency is selectable between 156 kHz and 1.25 MHz with EEPROM bit <BOOST_FREQ[1:0]>. When <EN_BOOST> EEPROM register bit is set to 1, then boost activates automatically when backlight is enabled.

In adaptive mode the boost output voltage is adjusted automatically based on LED driver headroom voltage. Boost output voltage control step size is, in this case, 125 mV, to ensure as small as possible driver headroom and high efficiency. Enabling the adaptive mode is done with <EN_ADAPT> EEPROM bit. If boost is started with adaptive mode enabled, then the initial boost output voltage value is defined with the <VBOOST[4:0]> EEPROM register bits in order to eliminate long output voltage iteration time when boost is started for the first time. Figure 12 shows the boost topology with the protection circuitry:

8.3.3.2 Protection

Three different protection schemes are implemented:

1. Overvoltage protection, limits the maximum output voltage.
   • Overvoltage protection limit changes dynamically based on output voltage setting.
   • Keeps the output below breakdown voltage.
   • Prevents boost operation if battery voltage is much higher than desired output.
2. Overcurrent protection, limits the maximum inductor current.
3. Duty cycle limiting.

8.3.3.3 Manual Output Voltage Control

User can control the boost output voltage with <VBOOST[4:0]> EEPROM register bits when adaptive mode is disabled.

8.3.3.4 Adaptive Boost Control

Adaptive boost control function adjusts the boost output voltage to the minimum sufficient voltage for proper LED driver operation. The output with highest V_F LED string is detected and boost output voltage adjusted accordingly. Driver headroom can be adjusted with <DRIVER_HEADR[2:0]> EEPROM bits from approximately 300 mV to 1200 mV. Boost adaptive control voltage step size is 125 mV. Boost adaptive control operates similarly with and without PSPWM.

Figure 13. Boost Adaptive Control Principle with PSPWM

8.3.4.1 LED Fault Detection

With LED fault detection, the voltages across the LED drivers are constantly monitored. LED fault detection is enabled with <EN_LED_FAULT> EEPROM bit. Shorted or open LED string is detected.

If LED fault is detected:

• The corresponding LED string is taken out of boost adaptive control loop;
• Fault bits are set in the fault register to identify whether the fault has been open/short and how many strings are faulty; and
• Fault open-drain pin is pulled down.

LED fault sensitivity can be adjusted with <LED_FAULT_THR> EEPROM bit which sets the allowable variation between LED output voltage to 3.3 V or 5.3 V. Depending on application and how much variation there can be in normal operation between LED string forward voltages this setting can be adjusted.

Fault is cleared by setting EN pin low or by reading the fault register.

8.3.4.2 Undervoltage Detection

The LP8551 has detection for too-low VIN voltage. Threshold level for the voltage is set with EEPROM register bits as seen in Table 2:

When undervoltage is detected, the LED outputs and boost shut down, the FAULT pin is pulled down, and corresponding fault bit is set in fault register. LEDs and boost starts again when the voltage has increased above the threshold level. Hysteresis is implemented to threshold level to avoid continuous triggering of fault when threshold is reached.

Fault is cleared by setting EN pin low or by reading the fault register.

8.3.4.3 Overcurrent Protection

The LP8551 has detection for too-high loading on the boost converter. When overcurrent fault is detected, the LP8551 shuts down.

Fault is cleared by setting EN pin low or by reading the fault register.

8.3.4.4 Device Thermal Regulation

The LP8551 has an internal temperature sensor which can be used to measure the junction temperature of the device and protect the device from overheating. During thermal regulation, LED PWM is reduced by 2% of full scale per °C whenever the temperature threshold is reached. Temperature regulation is enabled automatically when chip is enabled. 11-bit temperature value can be read from Temp MSB and Temp LSB registers, MSB should be read first. Temperature limit can be programmed in EEPROM as shown in the following table.

Thermal regulation function does not generate fault signal.

8.3.4.5 Thermal Shutdown

If the LP8551 reaches thermal shutdown temperature (150°C), the LED outputs and boost shut down to protect it from damage. Also the FAULT pin is pulled down to indicate the fault state. The device activates again when temperature drops below 130°C degrees.

Fault is cleared by setting EN pin low or by reading the fault register.

8.5.1.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCLK). These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the SCLK. The LP8551 is always a slave device.

8.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock SCLK. Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCLK and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCLK state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 15. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process.

Figure 16. Start and Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCLK) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCLK is high indicates a Stop Condition.

Figure 17. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle.

8.5.1.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

8.5.1.4 “Acknowledge After Every Byte” Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

8.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP8551 operates as a slave device with 7-bit address combined with data direction bit. Slave address is 2Ch as 7-bit or 58h for write and 59h for read in 8-bit format.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 18. I²C Chip Address

8.5.1.6 Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master sends further data bytes the control register address is incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition.

8.5.1.7 Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

Table 3. Data Read and Write Cycles

8.5.1.8 Register Read and Write Detail

Figure 19. LP8551 Register Write Format

Figure 20. LP8551 Register Read Format

8.6.1.1 Brightness Control

Address 00h

Reset value 0000 0000b

8.6.1.2 Device Control

Address 01h

Reset value 0000 0000b

8.6.1.3 Fault

Address 02h

Reset value 0000 0000b

8.6.1.4 Identification

Address 03h

Reset value 1111 1100b

8.6.1.5 Direct Control

Address 04h

Reset value 0000 0000b

8.6.1.6 Temp MSB

Address 05h

Reset value 0000 0000b

8.6.1.7 Temp LSB

Address 06h

Reset value 0000 0000b

8.6.1.8 EEPROM Control

Address 72h

Reset value 0000 0000b

Programming sequence (program data permanently from registers to NVM):

1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h)
2. Write data to EEPROM registers (address A0h…A7h)
3. Write EE_INIT to 1 in address 72h. (04h to address 72h)
4. Write EE_PROG to 1 and EE_INIT to 0 in address 72h. (02h to address 72h)
5. Wait 200 ms.
6. Write EE_PROG to 0 in address 72h. (00h to address 72h)

Read sequence (load data from NVM to registers):

1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h).
2. Write EE_INIT to 1 in address 72h. (04h to address 72h)
3. Write EE_READ to 1 and EE_INIT to 0 in address 72h. (01h to address 72h)
4. Wait 200 ms.
5. Write EE_READ to 0 in address 72h. (00h to address 72h)

8.6.2.1 EEPROM Register Map

8.6.2.2 EEPROM Address 0

Address A0h

8.6.2.3 EEPROM Address 1

Address A1h

8.6.2.4 EEPROM Address 2

Address A2h

8.6.2.5 EEPROM Address 3

Address A3h

8.6.2.6 EEPROM Address 4

Address A4h

8.6.2.7 EEPROM Address 5

Address A5h

8.6.2.8 EEPROM Address 7

Address A7h