SBOSA93C May 2023 – June 2024 OPT4001-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Output registers always contain the most recent light measurement. Along with the output registers, there are three more shadow registers that have data from the previous three measurements. For every new measurement, the data on the three shadow registers are updated to contain the most recent measurements, discarding the oldest measurement similar to a FIFO scheme. These shadow registers, along with the output registers, act like a FIFO with a depth of 4. The INT pin can be configured (as shown in Figure 6-2) to generate an interrupt for every measurement, or can be configured to generate an interrupt every four measurements using the INT_CFG register. In this manner, the controller reading data from the OPT4001-Q1 minimizes the number of interrupts by a factor of 4 and is still provided access to all four measurements between the interrupts. By using burst read mode, the output and FIFO registers can be read out with minimal I2C clocks.