SLLSEA0I February   2012  – January 2021 SN6501

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Push-Pull Converter
      2. 7.3.2 Core Magnetization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up Mode
      2. 7.4.2 Operating Mode
      3. 7.4.3 Off-Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SN6501 Drive Capability
        2. 8.2.2.2 LDO Selection
        3. 8.2.2.3 Diode Selection
        4. 8.2.2.4 Capacitor Selection
        5. 8.2.2.5 Transformer Selection
          1. 8.2.2.5.1 V-t Product Calculation
          2. 8.2.2.5.2 Turns Ratio Estimate
          3. 8.2.2.5.3 Recommended Transformers
      3. 8.2.3 Application Curve
      4. 8.2.4 Higher Output Voltage Designs
      5. 8.2.5 Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Application Information

The SN6501 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive, comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output signals which alternately turn the two output transistors on and off.

GUID-39D8C56C-A4FB-4256-804A-5E84B3DDB768-low.gifFigure 8-1 SN6501 Block Diagram And Output Timing With Break-Before-Make Action

The output frequency of the oscillator is divided down by an asynchronous divider that provides two complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gate-drive signals for the output transistors Q1 and Q2. As shown in Figure 8-2, before either one of the gates can assume logic high, there must be a short time period during which both signals are low and both transistors are high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of the primary.

GUID-C121A1C5-A859-48FF-AC2B-5885FAA62830-low.gifFigure 8-2 Detailed Output Signal Waveforms