SNLS692B December   2021  – December 2023 SN75LVPE5421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUA|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-20210120-CA0I-LLGZ-GZF1-CPQJKH9CQJHG-low.gif Figure 4-1 RUA Package, 42-Pin WQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
MODE 41 I, 5-level Sets device control configuration modes. The 5-level IO pin is defined in Table 6-1. The pin can be exercised at device power up or in normal operation mode.
L0: Pin Mode – device control configuration is done solely by strap pins.
L1 or L2: SMBus/I2C Mode – device control configuration is done by an external controller with SMBus/I2C primary. This pin along with ADDR pin sets devices secondary address.
L3 and L4 (Float): RESERVED – TI internal test modes.
EQ0 /ADDR 40 I, 5-level In Pin Mode:
The EQ0 and EQ1 pins sets receiver linear equalization CTLE (AC gain) for all channels according to Table 6-2. These pins are sampled at device power-up only.
In SMBus/I2C Mode:
The ADDR pin in conjunction with MODE pin sets SMBus / I2C secondary address according to Table 6-5. The pin is sampled at device power-up only.
EQ1 20 I, 5-level
GAIN /SDA 1 I, 5-level / IO In Pin Mode:
Flat gain (broadband gain – DC and AC) from the input to the output of the device for all channels. Note: the device also provides AC (high frequency) gain in the form of equalization controlled by EQ pins or SMBus/I2C registers. The pin is sampled at device power-up only.
In SMBus/I2C Mode:
3.3V SMBus/I2C data. External pullup resistor such as 4.7 kΩ required for operation.
GND EP, 6, 9, 16, 21, 30, 39 P Ground reference for the device.
EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return for the device. The EP should be connected to one or more ground planes through the low resistance path. A via array provides a low impedance path to GND. The EP also improves thermal dissipation.
PD 18 I, 3.3V LVCMOS 2-level logic controlling the operating state of the redriver. Active in both Pin Mode and SMBus/I2C Mode. The pin is used part of PCIe RX_DET state machine as outlined in Table 6-4.
High: power down for all channels
Low: power up, normal operation for all channels
RSVD1, 2 2, 12 — Reserved pins – for best signal integrity performance connect the pins to GND. Alternate option would be 0 Ω resistors from pins to GND.
RX_DET /SCL 42 I, 5-level / IO In Pin Mode:
Sets receiver detect state machine options according to Table 6-4. The pin is sampled at device power-up only.
In SMBus/I2C Mode:
3.3V SMBus/I2C clock. External pullup resistor such as 4.7 kΩ required for operation.
RXA0N 37 I Inverting differential RX input – Port A, Channel 0.
RXA0P 38 I Noninverting differential RX input – Port A, Channel 0.
RXA1N 33 I Inverting differential RX input – Port A, Channel 1.
RXA1P 34 I Noninverting differential RX input – Port A, Channel 1.
RXA2N 28 I Inverting differential RX input – Port A, Channel 2.
RXA2P 29 I Noninverting differential RX input – Port A, Channel 2.
RXA3N 24 I Inverting differential RX input – Port A, Channel 3.
RXA3P 25 I Noninverting differential RX input – Port A, Channel 3.
RXB0N 35 I Inverting differential RX input – Port B, Channel 0.
RXB0P 36 I Noninverting differential RX input – Port B, Channel 0.
RXB1N 31 I Inverting differential RX input – Port B, Channel 1.
RXB1P 32 I Noninverting differential RX input – Port B, Channel 1.
RXB2N 26 I Inverting differential RX input – Port B, Channel 2.
RXB2P 27 I Noninverting differential RX input – Port B, Channel 2.
RXB3N 22 I Inverting differential RX input – Port B, Channel 3.
RXB3P 23 I Noninverting differential RX input – Port B, Channel 3.
SEL 17 I, 3.3V LVCMOS Selects the mux path. Active in both Pin Mode and SMBus/I2C Mode. The pin has a weak internal pull-down resistor. Note: the SEL pin must be exercised in system implementations for mux selection between Port A vs Port B. The pin is used for PCIe RX_DET state machine as outlined in Table 6-4.
L: Port A selected.
H: Port B selected.
TX0N 4 O Inverting differential TX output, Channel 0.
TX0P 3 O Noninverting differential TX output, Channel 0.
TX1N 8 O Inverting differential TX output, Channel 1.
TX1P 7 O Noninverting differential TX output, Channel 1.
TX2N 11 O Inverting differential TX output, Channel 2.
TX2P 10 O Noninverting differential TX output, Channel 2.
TX3N 15 O Inverting differential TX output, Channel 3.
TX3P 14 O Noninverting differential TX output, Channel 3.
TEST 19 O TI internal test pin. Keep no connect.
VCC 5, 13 P Power supply, VCC = 3.3V ± 10%. The VCC pins on this device should be connected through a low-resistance path to the board VCC plane.
(1) I = input, O = output, P = power, GND = ground