SBOS778D April   2016  – April 2021 THS4551

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Companion Devices
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential Open-Loop Gain and Output Impedance
      2. 9.3.2 Setting Resistor Values Versus Gain
      3. 9.3.3 I/O Headroom Considerations
      4. 9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 9.4.2 Operation from a Differential Input to a Differential Output
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 9.4.3 Input Overdrive Performance
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Noise Analysis
      2. 10.1.2 Factors Influencing Harmonic Distortion
      3. 10.1.3 Driving Capacitive Loads
      4. 10.1.4 Interfacing to High-Performance Precision ADCs
      5. 10.1.5 Operating the Power Shutdown Feature
      6. 10.1.6 Designing Attenuators
      7. 10.1.7 The Effect of Adding a Feedback Capacitor
    2. 10.2 Typical Applications
      1. 10.2.1 An MFB Filter Driving an ADC Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Analysis
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Example
    3. 12.3 EVM Board
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TINA-TI Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision C (July 2017) to Revision D (April 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added the Device Information table to the Description sectionGo
  • Moved the Low-Power ADCs Supported by the THS4551 table to the Device Comparison sectionGo
  • Removed the IIB input bias current (positive current out-of-node) minimum limits in the Electrical Characteristics: (VS+) – (VS–) = 5 V sectionGo
  • Removed the IIB input bias current (positive current out-of-node) minimum limits in the Electrical Characteristics: (VS+) – (VS–) = 3 V sectionGo

Changes from Revision B (November 2016) to Revision C (July 2017)

  • Changed 47k Ohms , 1.3 pF to 150k Ohms , 7 pF in the Section 7.6 table Go

Changes from Revision A (August 2016) to Revision B (November 2016)

  • Changed TINA to TINA-TI throughout document Go
  • Changed Trimmed-Supply Current and Input Offset Voltage Drift Features bulletsGo
  • Added pin 1 indicator to RGT and RUN pin out drawingsGo
  • Changed pins IN–, OUT+, OUT–, and IN+ in DGK packageGo
  • Added second row and footnote 2 to Voltage parameter of Absolute Maximum Ratings tableGo
  • Added package differences and footnote 3 to ESD Ratings tableGo
  • Changed footnotes 1 and 2 in 5-V Electrical Characteristics tableGo
  • Added test conditions to AOL parameter in 5-V Electrical Characteristics tableGo
  • Changed Internal feedback trace resistance parameter test conditions and typical and maximum specifications in test level A row, added test level B rowGo
  • Changed Internal feedback trace resistance mismatch parameter test conditions and minimum and maximum specifications in test level A row, added test level B row and footnote 5 Go
  • Changed Input offset voltage drift parameter Go
  • Changed IIB parameter minimum and maximum specifications in last three rows Go
  • Changed Input bias current drift parameter test conditions and specifications Go
  • Added Input offset current drift parameter test conditions, minimum and maximum specifications, and test level value to second rowGo
  • Changed test conditions of Common-mode input, low and Common-mode input, high parameters Go
  • Changed test conditions of Continuous output current and Linear output current parameters Go
  • Changed typical specification of IQ parameterGo
  • Changed test conditions of Enable voltage threshold and Disable voltage threshold parametersGo
  • Changed specifications of Power-down quiescent current parameter Go
  • Added second row to Default voltage offset parameterGo
  • Changed Common-mode loop supply headroom to negative supply parameter test conditionsGo
  • Changed test conditions and maximum specifications of Common-mode loop supply headroom to positive supply parameterGo
  • Changed ICC value in footnote 5 Go
  • Added test conditions to DC Performance, AOL parameterGo
  • Changed Internal feedback trace resistance parameter test conditions and typical and maximum specifications in test level A row, added test level B row Go
  • Changed Internal feedback trace resistance mismatch parameter test conditions and minimum and maximum specifications in test level A row, added test level B row and footnote 5 Go
  • Changed Input offset voltage drift parameter test conditions in first row, added second rowGo
  • Changed minimum and maximum specifications in last three rows of IIB parameterGo
  • Changed Input bias current drift parameter test conditionsGo
  • Added second row to Input offset current drift parameter Go
  • Changed test conditions of Common-mode input, low and Common-mode input, high parametersGo
  • Changed test conditions of Continuous output current and Linear output current parameters Go
  • Changed test conditions of Enable voltage threshold and Disable voltage threshold parametersGo
  • Changed IQ(PD) parameter specificationsGo
  • Added second row to Default voltage offset parameterGo
  • Changed Common-mode loop supply headroom to negative supply parameter test conditionsGo
  • Changed Common-mode loop supply headroom to positive supply parameter test conditions and maximum specifications Go
  • Changed conditions of Figure 7-49 to Figure 7-54 Go
  • Added simulation file and simulation circuit cross-references throughout documentGo
  • Changed Single-Ended Source to a Differential Gain of a 1-V/V Test Circuit figureGo
  • Changed fifth bullet to Example Characterization Circuits sectionGo
  • Changed Output Common-Mode Measurements figureGo
  • Changed I/O Headroom Considerations section: changed last sentence of first paragraph, changed fifth paragraph, clarifications added throughout sectionGo
  • Changed Output DC Error and Drift Calculations and the Effect of Resistor Imbalances section: description of input impedance matching and Worst-Case Output VOD Drift Band table and reference descriptionGo
  • Changed main Device Functional Modes section: changed value of PD pin voltage Go
  • Changed positive supply value in AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions section Go
  • Changed the minimum value for single-supply operation in the Operating the Power Shutdown Feature sectionGo
  • Changed Designing Attenuators section: changed low dc noise gain to low-noise gain in first paragraph, changed noise to noise gain in second paragraphGo
  • Changed Open-Loop Gain and Phase TINA-TI™ Simulation Setup figureGo
  • Added SBOS476, SBOC466, SBOC463, SBOC467, SBOS460, SBOC477, SBOC472, SLOC341, SBOC469, SBOC462, SBOC461, SBOC465, SBOC464, SBOC475, SBOC474, SBOC471, SBOC459, SBOC470, SBOC468, and SBOC473 to Related Documentation section Go

Changes from Revision * (April 2016) to Revision A (August 2016)

  • Released to production Go