4 Revision History
Changes from A Revision (May 2013) to B Revision
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Changed format to meet latest data sheet standards; added Applications and Implementation, Power Supply Recommendations, and Layout sections, moved existing sectionsGo
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Changed 8-bit pulse width modulation to 12-bit pulse width modulation in Description section Go
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Changed tH0 and tH1 parameter units from µs to ns in Recommended Operating Conditions table Go
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Changed Figure 8: deleted top SDO, changed bottom SDO to OUTn Go
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Changed Figure 11: deleted extraneous breaks in traces, extraneous data call-outs, and tH1 on GSLAT trace, changed data transfer trace note to Internal to 1st Device and 1st Data to 47th Data in 48-Bit Shift Register LSB traceGo
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Changed functional block diagram: changed Upper 8 Bits to Upper 12 Bits on 48-Bit Shift Register blockGo
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Added Grayscale (GS) Control, EasySet and Shunt Regulator, and No Limit Cascading sectionsGo
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Changed Connector Design title Go
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Changed Figure 13: changed OUTn traces GSDATA = 4093 and GSDATA = 4094 Go
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Changed description of the Data ‘0’ and Data ‘1’ Write Sequence (Data Write Sequence) section Go
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Changed title of Controlling Devices Connected in Series sectionGo
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Changed Data 101 to Data 1010 in Figure 18 Go
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Changed eight MSBs to 12 MSBs in third sentence of the Register and Data Latch Configuration sectionGo
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Changed Figure 21: corrected 3AAh bit set sequenceGo
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Changed Figure 26: changed number of LEDs in optional dashed boxGo
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Changed Table 7: changed all values in RVCC column and first and last values in Resistor Wattage columnGo
Changes from * Revision (March 2013) to A Revision
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Changed second paragraph of Grayscale (GS) Function (PWM Control) sectionGo
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Changed tCYCLE setting range in Data Transfer Rate (tCYCLE) Measurement Sequence sectionGo
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Updated Figure 18Go
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Updated Figure 21 and Table 3Go