SNIS217C december   2020  – may 2023 TMP139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down and Device Reset
      3. 7.3.3 Temperature Result and Limits
      4. 7.3.4 Bus Reset
      5. 7.3.5 Interrupt Generation
      6. 7.3.6 Parity Error Check
      7. 7.3.7 Packet Error Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Mode
      2. 7.4.2 Serial Address
      3. 7.4.3 I2C Mode Operation
        1. 7.4.3.1 Host I2C Write Operation
        2. 7.4.3.2 Host I2C Read Operation
        3. 7.4.3.3 Host I2C Read Operation in Default Read Address Pointer Mode
        4. 7.4.3.4 Switching from I2C Mode to I3C Basic Mode
      4. 7.4.4 I3C Basic Mode Operation
        1. 7.4.4.1 Host I3C Write Operation without PEC
        2. 7.4.4.2 Host I3C Write Operation with PEC
        3. 7.4.4.3 Host I3C Read Operation without PEC
        4. 7.4.4.4 Host I3C Read Operation with PEC
        5. 7.4.4.5 Host I3C Read Operation in Default Read Address Pointer Mode
      5. 7.4.5 In Band Interrupt
        1. 7.4.5.1 In Band Interrupt Arbitration Rules
        2. 7.4.5.2 In Band Interrupt Bus Transaction
      6. 7.4.6 Common Command Codes Support
        1. 7.4.6.1 ENEC CCC
        2. 7.4.6.2 DISEC CCC
        3. 7.4.6.3 RSTDAA CCC
        4. 7.4.6.4 SETAASA CCC
        5. 7.4.6.5 GETSTATUS CCC
        6. 7.4.6.6 DEVCAP CCC
        7. 7.4.6.7 SETHID CCC
        8. 7.4.6.8 DEVCTRL CCC
      7. 7.4.7 I/O Operation
      8. 7.4.8 Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1 Enabling Interrupt Mechanism
      2. 7.5.2 Clearing Interrupt
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = −40°C to +125°C, VDDIO = 0.95 V to 1.05 V and VDDSPD = 1.7 V to 1.98 V (unless noted); typical specification are at TA = 25°C, VDDIO = 1 V and VDDSPD =1.8 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE INPUT
TERR Temperature Accuracy +75°C to +95°C ±0.25 ±0.5 °C
–40°C to +125°C ±0.25 ±0.75 °C
TRES Resolution 1 LSB (11-bit) 0.25 °C
TREPEAT Repeatability(1) 1 LSB
tACT Active conversion time 5.5 ms
tCONV Conversion interval 125 ms
THYST Temperature Hysteresis 1 °C
DIGITAL INPUT/OUTPUT
CIN Input capacitance(2) Input capacitance (SCL and SDA) 4 pF
RON Output pullup and pulldown driver impedance SDA pin 20 100 Ω
ILI Leakage input current -1 0 1 µA
ILO Leakage output current -1 0 1 µA
VIL Low-level input logic –0.3 0.3 V
VIH High-level input logic 0.7 1.35 V
VHYS Input voltage hysteresis SCL and SDA pins 60 100 mV
VOL Low-level output logic SDA pin, IOL = –3 mA 0 0.3 V
VOH High-level output logic SDA pin, IOH = 3 mA 0.75 V
SLEW_RATE Output slew rate(2) SDA pin 0.1 1.0 V/ns
POWER SUPPLY
IQ Average current (serial bus inactive)  125-ms conversion interval 8.3 12.4 µA
IDDR Average current (read operation)  125-ms conversion interval, read temperature register, fSCL = 12.5 MHz 8.3 µA
IDDW Average current (write operation)  125-ms conversion interval, write alert register, fSCL = 12.5 MHz 8.3 µA
IACT Active current During 5.5-ms active conversion 99 140 µA
IDD1 Standby current Between active conversion during continuous conversion 4 6.5 µA
VPON Power-on reset threshold Monotonic rise between VPON and VDDSPD(MIN) 1.6 V
VPOFF Power-off reset threshold for warm power on cycle No ringback above VPOFF 0.3 V
tINIT Initialization time after Power-on reset(2) Figure 7-2 10.0 ms
tPOFF Warm power cycle off time(2) Figure 7-3 1.0 ms
tSENSE_SA Time from valid VDDSPD supply to sense SA pin for LID code assignment(2) Figure 7-2 5.0 ms
tRST Device reinitialization time(2)(3) 40 µs
(1) Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.
(2) Parameter is specified by design
(3) Parameter is specified for RSTDAA Common Command Code