SBOSA15A september 2022 – may 2023 TMP1827
PRODUCTION DATA
In the combined IO and resistor address mode, the IO0 and IO1 pins are used along with the resistor connected between ADDR pin and ground. Figure 9-7 shows the 8-bit address with the lower 4 bits decoded from the resistor connected, followed by 2 bits decoded from the IO0 and IO1 pins which may be connected to either VDD/SDQ for logic '1' or GND for logic '0', which is overlaid on the contents of the short address register. TI recommends to use a 20 KΩ resistor to be placed between the IO and VDD/SDQ to prevent a supply shot in case the IO pin is accidentally set to zero in output mode.
After having FLEX_ADDR_MODE as '00b', the host must set the bits as '11b' in the device configuration-2 register which enables the device to sample the ADDR pin to identify the resistor connected, followed by sampling of the IO0 and IO1 to configure the short address. If the bit field value has already been updated in the non-volatile storage, then the device shall automatically latch the pins, run the resistor decoder, and update the value in the short address register on power up.
The host controller must place the device in shut down mode and idle the bus for tRESDET, for the device to decode the resistor address.
This mode is useful when the application requires placing up to 64 devices on a single PCB, as it allows for easy expansion using a combined approach of IO and resistor decoding while enabling IO2 and IO3 to function as general-purpose input and output pins. This mode may also be used for position identification as no two devices may have the same short address.