SLUSF08A March   2024  – September 2024 TPS1213-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving
        1. 7.3.2.1 Using Low Power Bypass FET (G2 drive) for Load Capacitor Charging
        2. 7.3.2.2 Using Main FET (G1 Drive) Gate Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 State Transition Timing Diagram
      3. 7.4.3 Power Down
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 Low Power Mode
      6. 7.4.6 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application 1: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application 2: Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 8.3.1 Design Requirements
      2. 8.3.2 External Component Selection
      3. 8.3.3 Application Curves
    4. 8.4 TIDA-020065: Automotive Smart Fuse Reference Design Driving Power At All Times (PAAT) Loads With Automatic Load Wakeup, Output Bulk Capacitor Charging, Bi-directional Current Sensing and Software I2t
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGX|19
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.5 Low Power Mode

The device transitions from shutdown to low power mode when EN/UVLO is driven high ( > V(ENR)) and LPM is driven low for > 500µs simultaneously.

The device can also transition from active mode to low power mode when LPM is pulled low. When entering from active mode to low power mode, LPM and INP signal sequencing consideration can be followed as per Figure 7-15. Pulling INP low before LPM results in main FET (G1 gate drive) turning OFF which can cause output voltage droop momentarily before bypass FET (G2 gate drive) turns ON. Pulling INP low after at least 10µs of LPM is pulled low makes a seamless transition from active to low power mode without any output voltage dip.

In this mode, charge pump and gate drivers are enabled. The main FET (G1 gate drive) is OFF and bypass FET (G2 gate drive) is turned ON and WAKE pin asserts high in this state. TPS12130-Q1 consumes low IQ of 35µA (typical) in low power mode.

The device transitions from low power mode to active mode when:

  • External Trigger: LPM is pulled high externally
  • Internal Trigger: Load current exceeds load wakeup trigger threshold (ILWU) set by Equation 4

After load current exceeds load wakeup threshold (ILWU), the device automatically turns OFF the bypass FET (G2 gate drive) and turns ON main FET (G1 gate drive) and WAKE asserts low indicating the exit from the low power mode.

The device waits for external LPM signal to go high to transition into Active mode.

Protections available in low power mode are:

  • Input UVLO: Bypass FET (G2 gate drive) is turned OFF when voltage on EN/UVLO falls below V(UVLOF) and FLT asserts low.
  • Charge pump UVLO: Bypass FET (G2 gate drive) is turned OFF when voltage between BST to SRC falls below V(BST_UVLOF) and FLT asserts low.
  • Short-circuit protection: If output short-circuit event occurs in low power mode then, the device automatically exits low power mode by turning OFF the bypass FET (G2 gate drive) and turning ON main FET (G1 gate drive) via the load wakeup functionality. In load wakeup state, if the voltage across CS+ and CS– exceeds the set short-circuit threshold (VSCP/LWU), main FET (G1 gate drive) is turned OFF and FLT asserts low. The subsequent operation is based on auto-retry or latch off as per the configuration.